E-beam Lithography Dithering for Wafer Throughput
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Solution Overview
Problem
Electron beam lithography systems face low wafer throughput, which is a significant obstacle for large-scale fabrication in the IC industry, especially due to the time-consuming process of writing patterns with small pixel sizes.
Innovation Solution
The implementation of a dithering method using a vertex map to convert IC design layout patterns from small pixel sizes to larger pixel sizes, allowing for on-line generation of patterned electron beam data, thereby increasing throughput by reducing data processing time and memory requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If small pixel sizes are used for pattern writing, then manufacturing precision is improved, but productivity deteriorates due to increased data processing time
Solution Approach 1:
The patent transforms the pixel size parameter from small to large through dithering processing. By converting the original small-pixel pattern into a large-pixel dithered pattern, the system achieves both high manufacturing precision (through accurate edge representation) and high productivity (through reduced data volume and faster writing speed).
Solution Approach 2:
The patent creates a dithered copy of the original pattern that preserves critical edge information while reducing overall data complexity. The dithered pattern serves as an alternative representation that maintains manufacturing precision while enabling faster processing and writing.
2Manufacturing precision
If small pixel sizes are used for pattern writing, then manufacturing precision is improved, but loss of time increases due to offline processing requirements
Solution Approach 1:
The patent performs dithering processing in advance to convert the pattern from small pixels to large pixels before writing. This preliminary transformation reduces the computational burden during actual writing operations, eliminating the need for time-consuming offline processing while maintaining precision.
Solution Approach 2:
By changing the pixel size parameter through dithering, the system transforms a precision-critical small-pixel problem into a more efficient large-pixel representation that requires less processing time while preserving the necessary manufacturing precision.
3Manufacturing precision
If small pixel sizes are used for pattern writing, then manufacturing precision is improved, but device complexity increases due to memory requirements
Solution Approach 1:
The patent changes the spatial resolution parameter by transforming small pixels into large pixels through dithering. This parameter transformation significantly reduces memory requirements while maintaining pattern accuracy through intelligent error diffusion and edge-preserving algorithms.
Solution Approach 2:
The system creates a dithered copy that preserves essential pattern information in a more compact form. This copied representation maintains manufacturing precision while requiring less memory storage and processing capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances wafer throughput by streamlining data processing and reducing edge error propagation, improving feature critical dimension uniformity and overlay accuracy, and enabling faster pattern writing without the need for extra edge map data or offline processing.
Implementation Method 1
A method of exposing the resist film deposited on the substrate. A patterned electron beam data is generated through the vertex map.
Data Source
AI summary
The present disclosure provides a dithering method of increasing wafer throughput by an electron beam lithography system. The dithering method generates an edge map from a vertex map. The vertex map is generated from an integrated circuit design layout (such as an original pattern bitmap). A gray map (also referred to as a pattern gray map) is also generated from the integrated circuit design layout. By combining the edge map with the gray map, a modified integrated circuit design layout (modified pattern bitmap) is generated for use by the electron beam lithography system.