Electron Beam Lithography Wafer Throughput Optimization
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Solution Overview
Problem
The electron beam lithography system faces a significant challenge in wafer throughput, which hampers large-scale fabrication in the IC industry due to the complexity and inefficiency of the scanning process.
Innovation Solution
The implementation of a method that optimizes wafer throughput by utilizing the maximum scan width (MSW) of the electron beam writer system, either by constraining the IC design field size to natural integer multiples of the MSW or by rearranging scan lane data during exposure to maximize the use of the MSW, thereby reducing scan time and increasing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If electron beam lithography is used to scale down feature size, then geometry size is decreased, but wafer throughput is reduced
Solution Approach 1:
The patent divides the writing area into multiple segments (first writing area and second writing area) that can be processed independently and simultaneously. By segmenting the exposure task across multiple regions with different scanning parameters, the system achieves parallel processing that increases overall wafer throughput while maintaining the required geometry precision.
2Productivity
If scanning process is optimized to increase wafer throughput, then productivity is improved, but scan time increases
Solution Approach 1:
The patent dynamically adjusts scanning parameters (scanning speed, beam current, focus) for different writing areas based on real-time requirements. By making the scanning process adaptive rather than static, the system optimizes the balance between throughput and scan time, allowing faster scanning in non-critical areas while maintaining precision where needed.
Solution Approach 2:
The patent changes multiple scanning parameters simultaneously (scanning speed, beam current, focus position) to optimize the exposure process. By varying these parameters across different writing areas and during the scanning process, the system achieves higher throughput without proportionally increasing scan time, as each parameter change contributes to efficient resource utilization.
3Productivity
If multiple writing areas are scanned with different parameters to increase throughput, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent designs the electron beam writing system to perform multiple functions using the same core components. The same electron beam source and scanning mechanism handle different writing areas with varying parameters, eliminating the need for separate dedicated systems for each region. This multi-functionality increases throughput without proportionally increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a substantial reduction in scan time and a significant increase in throughput, with examples showing up to a 67% savings in scan time and a corresponding tripling of throughput, allowing for more efficient processing of wafers.
Implementation Method 1
an electron beam writer system exposes a photo resist film on a wafer substrate by scanning the wafer substrate with electron beams
Data Source
AI summary
The present disclosure provides a method of increasing the wafer throughput by an electron beam lithography system. The method includes scanning a wafer using the maximum scan slit width (MSSW) of the electron beam writer. By constraining the integrated circuit (IC) field size to allow the MSSW to cover a complete field, the MSSW is applied to decrease the scan lanes of a wafer and thereby increase the throughput. When scanning the wafer with the MSSW, the next scan lane data can be rearranged and loaded into a memory buffer. Thus, once one scan lane is finished, the next scan lane data in the memory buffer is read for scanning.