E-beam In-chip Overlay Mark for Reduced Silicon Area
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Solution Overview
Problem
Current overlay marks in semiconductor integrated circuit fabrication occupy large chip areas due to limitations in optical tool resolution, increasing manufacturing costs and making it challenging to integrate additional marks, especially as feature sizes shrink, necessitating a more efficient method for in-chip overlay measurement and control with reduced silicon area usage.
Innovation Solution
The implementation of electron-based overlay marks and a system that utilizes an electron-based metrology technique, including an electron microscope, to measure and analyze overlay errors with higher resolution, allowing for smaller mark sizes and reduced wafer area usage, while enabling simultaneous critical dimension measurement and overlay analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If optical-based overlay marks are used, then overlay measurement can be performed, but the mark size becomes large occupying excessive chip area
Solution Approach 1:
The patent replaces optical-based overlay measurement with electron-based overlay measurement. Specifically, electron microscopes or electron beam systems are used instead of optical microscopes to detect overlay marks, enabling the use of much smaller mark sizes while maintaining measurement capability. This substitution of detection methodology allows overlay marks to be shrunk significantly without losing measurement precision.
Solution Approach 2:
The patent changes the detection parameter from optical wavelength to electron beam wavelength. By using electron beams with much shorter effective wavelengths compared to optical light, the resolution limit is overcome, allowing smaller overlay marks to be detected with the same or better precision. This parameter change in the detection system enables the reduction of mark size on the chip.
2Area of moving object
If overlay mark size is reduced to save chip area, then chip area is saved, but measurement accuracy deteriorates with optical tools
Solution Approach 1:
The patent substitutes electron-based detection systems for optical detection systems to maintain measurement accuracy with smaller marks. The electron beam provides higher resolution capability that allows accurate measurement of reduced-size overlay marks, thus preserving measurement precision while enabling area reduction.
3Reliability
If additional overlay marks are added to circuit areas, then overlay monitoring coverage is improved, but place and route complexity increases
Solution Approach 1:
The patent divides the overlay measurement function into multiple small, distributed overlay marks that can be independently placed throughout the chip. These segmented marks can be integrated into different circuit areas without creating complex interconnections, as each mark is a standalone measurement feature rather than a connected structure.
Solution Approach 2:
By changing the detection method to electron-based measurement, the patent enables the use of multiple small marks without increasing complexity. The electron beam can selectively target and measure each small mark independently, allowing dense distribution of marks across the chip without requiring complex routing or interconnection structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for accurate and efficient overlay error determination with reduced wafer area usage, lower manufacturing costs, and improved measurement accuracy by using electron-based marks that are smaller than optical-based marks, addressing the challenge of shrinking feature sizes and overlay mark size constraints.
Implementation Method 1
an electron beam is directed to the overlay marks
Data Source
AI summary
The present disclosure provides an integrated circuit structure that includes a semiconductor substrate having a first region and a second region having an area less than about 10 micron×10 micron; a first material layer over the semiconductor substrate and patterned to have a first circuit feature in the first region and a first mark in the second region; and a second material layer over the first material layer and patterned to have a second circuit feature in the first region and a second mark in the second region. The first mark includes first mark features oriented in a first direction, and second mark features oriented in a second direction perpendicular to the first direction. The second mark includes third mark features oriented in the first direction, and fourth mark features oriented in the second direction.