Embedded Controller Firmware Flashing via Buffer Verification

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Solution Overview

Problem

Existing information handling systems lack secure methods for flashing embedded controllers, particularly in computing environments, where firmware updates need to be verified and stored securely to prevent malicious code execution and ensure system integrity.

Innovation Solution

A method is introduced where an embedded controller receives a firmware update from a central processing unit, stores it in a buffer region of a flash memory medium, verifies it using cryptographic functions, and upon verification, moves it to a primary region, while bypassing the platform controller hub to enhance security and prevent unauthorized access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the EC firmware update is stored and verified through the platform controller hub (PCH) using the second bus, then the system maintains standard communication protocols and compatibility, but the security is compromised and unauthorized access may occur

Engineering Contradiction:
Improvefirmware update securityVSAvoidbus bypass mechanism
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a buffer region as an intermediary storage location between the EC and flash memory medium. The EC stores firmware updates in this buffer region and verifies them before moving to the primary region, creating a secure intermediate zone that prevents direct unauthorized access while maintaining the standard bus architecture for compatibility

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The flash memory medium is segmented into distinct regions: a buffer region for temporary storage and verification of firmware updates, and a primary region for storing verified firmware. This segmentation isolates the verification process from the main firmware storage, enhancing security by preventing unauthorized modification of verified firmware while maintaining standard communication protocols

Inventive Principle:
Principle #1Segmentation

2Reliability

If the EC directly accesses the flash memory medium via the first bus bypassing the PCH, then the security is enhanced and unauthorized access is prevented, but the device complexity increases

Engineering Contradiction:
Improvefirmware update integrityVSAvoidflash access procedure
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The EC performs preliminary verification of the firmware update in the buffer region before moving it to the primary region. This preliminary action ensures that only verified and authenticated firmware is stored in the primary region, maintaining firmware integrity while using a standardized two-step process that balances security with ease of operation

Inventive Principle:
Principle #10Preliminary action

3Reliability

If cryptographic verification is performed on the EC firmware update, then the system integrity is ensured and malicious code is prevented, but the processing time increases

Engineering Contradiction:
Improvesystem integrityVSAvoidverification time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The cryptographic verification is performed preliminarily in the buffer region before the firmware is moved to the primary region. By performing this verification early in the update process, the system ensures integrity without delaying the overall flashing process, as the verification occurs during the normal update sequence rather than as an additional step

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11016755B2System and method to secure embedded controller flashing process
Publication Date: 2021.05.25 DELL PROD LP
  • US11016755B2 patent drawing
  • US11016755B2 patent drawing
  • US11016755B2 patent drawing

AI summary

Methods, systems, and computer programs for receiving, by an embedded controller (EC), an EC firmware update from a central processing unit (CPU); storing the EC firmware update into a buffer region of a flash memory medium via a first bus, the first bus communicatively coupling the EC and the flash memory medium; verifying the EC firmware update stored in the buffer region of the flash memory medium; and in response to verifying the EC firmware update: storing the verified EC firmware update into a primary region of the flash memory medium; and loading the verified EC firmware update from the primary region into an EC memory medium of the EC via the first bus.