ECaMS Processor Node Synchronization Without a Master Clock
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Solution Overview
Problem
Complex engine control and monitoring systems (ECaMS) lack effective synchronization methods between processor nodes, which can lead to unscheduled interruptions and failures, particularly in safety-critical applications like aeronautical gas turbine engines, where segregation of control and protection functions is essential.
Innovation Solution
A synchronization method that involves counting control cycle counts and transmission slot indexes at each processor node, with messages exchanged between nodes to adjust and synchronize their counts, using a ring network for communication, allowing for robust and adaptable synchronization without relying on a single clock source.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If processor nodes in ECaMS operate independently without a single clock source to increase adaptability, then system versatility is improved, but synchronization between nodes deteriorates leading to potential failures
Solution Approach 1:
The patent implements a feedback mechanism where each processor node transmits its control cycle count and transmission slot index to other nodes, and receives their corresponding data. Based on this feedback, nodes automatically adjust their counts and indexes to maintain synchronization. This feedback loop enables independent nodes to stay synchronized without requiring a centralized clock source, thus resolving the contradiction between adaptability and reliability.
Solution Approach 2:
The patent introduces control cycle counts and transmission slot indexes as intermediary parameters that mediate synchronization between independent processor nodes. These intermediaries allow nodes to exchange timing information and adjust their operations accordingly, enabling synchronization without a single master clock source, thereby maintaining both adaptability and reliability.
2Reliability
If processor nodes use separate clock sources to avoid single point of failure, then system reliability is improved, but timing consistency between nodes deteriorates
Solution Approach 1:
Nodes continuously exchange their control cycle counts and transmission slot indexes, creating a feedback mechanism that detects and corrects timing drift between nodes with separate clock sources. This feedback ensures timing consistency is maintained despite the absence of a unified clock source, preserving both reliability and stability.
Solution Approach 2:
The patent implements dynamic adjustment of control cycle counts and transmission slot indexes based on real-time synchronization needs. Nodes can adapt their timing parameters dynamically to maintain consistency, allowing the system to remain stable even with separate clock sources by continuously adjusting to maintain synchronization.
3Reliability
If ECaMS uses multiple segregated units for control and protection functions, then system safety is improved, but synchronization complexity increases
Solution Approach 1:
The patent creates a universal synchronization protocol using control cycle counts and transmission slot indexes that can be applied across all processor nodes regardless of their specific function (control or protection). This multi-functional approach allows segregated units to synchronize using the same mechanism, reducing overall synchronization complexity while maintaining safety through functional segregation.
Data Source
AI summary
Synchronisation methods for synchronising processor nodes of an Engine Control and Monitoring System (ECaMS) for an engine. A method comprises counting, at a first acquisition integrated circuit in a first processor node of the ECaMS, a first control cycle count, and storing at the first acquisition integrated circuit a first transmission slot index. The method further comprises counting a second control cycle count and storing a second transmission slot index at a second acquisition integrated circuit in a second processor node of the ECaMS. The method also comprises transmitting a message including the first control cycle count and transmission slot index from the first to second acquisition integrated circuits, and receiving the message at the second acquisition circuit. The method also comprises synchronising the first and second processor nodes using the first and second control cycle counts and transmission slot indexes.