Memory Circuit Testing With ECC-Adaptive Error Counting
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Solution Overview
Problem
Existing memory devices lack an optimized testing method that accounts for the level of error correction capability, particularly in systems utilizing off-chip error correction code (ECC) functions, leading to inefficiencies in defect detection and repair.
Innovation Solution
A memory device and testing method that includes a memory circuit generating test data, comparator groups for error detection, an error counter for symbol information generation, and an error determiner to generate a pass/fail signal based on error counts, optimizing the test scheme according to the ECC's level of error correction capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional testing method is used without considering ECC capability levels, then the testing process is simple, but the testing accuracy and defect detection reliability are insufficient
Solution Approach 1:
The patent applies parameter changes by adjusting the test scheme based on the ECC capability level parameter. When ECC capability is high, the test accepts more errors; when ECC capability is low, the test is more stringent. This dynamic parameter adjustment optimizes testing accuracy while adapting to different device configurations without requiring a completely different test structure.
Solution Approach 2:
The testing method dynamically adapts its criteria based on the detected ECC capability level of the memory device. The test automatically modifies its error tolerance and evaluation standards according to the device's actual capabilities, making the testing process flexible and context-aware rather than static and one-size-fits-all.
2Reliability
If the test scheme is optimized according to ECC capability level, then the defect detection reliability is improved, but the test complexity increases
Solution Approach 1:
The patent segments the testing process into distinct phases: first determining the ECC capability level, then selecting the appropriate test scheme based on that level. This segmentation allows the complex adaptive testing to be broken down into manageable steps, reducing the perceived complexity while maintaining high reliability through structured, level-based test selection.
Solution Approach 2:
The testing method performs a preliminary determination of the ECC capability level before executing the main defect detection tests. This preliminary action allows the system to pre-select the appropriate test scheme, ensuring that the main testing phase uses optimized criteria tailored to the device's capabilities, thereby improving reliability without adding significant overall complexity.
3Measurement precision
If multiple read operation periods are used for comprehensive error checking, then the error detection capability is improved, but the testing time increases
Solution Approach 1:
The patent changes the testing parameters (number of read operation periods, error thresholds, comparison criteria) based on the determined ECC capability level. For devices with higher ECC capabilities, the test may use fewer read periods or more lenient error thresholds, reducing testing time. For devices with lower ECC capabilities, the test uses more stringent criteria across multiple periods, ensuring thorough detection. This parameter adaptation balances detection capability with time efficiency.
Data Source
AI summary
Disclosed is a memory device and a testing method thereof, and the memory device may include a memory circuit generating a plurality of test data in a test mode, a plurality of comparator groups generating first comparison signals based on part of the plurality of test data and part of a plurality of reference data, and generating second comparison signals based on remaining test data and remaining reference data, an error counter generating first symbol information indicating a first number of errors occurring in the part of the plurality of test data, based on the first comparison signals, and generating second symbol information indicating a second number of errors occurring in the remaining test data, based on the second comparison signals, and an error determiner generating a pass/fail signal indicating whether the memory circuit is normal, based on the first and second symbol information.