ECC Memory Address Translation Using Addition-Based Checksum Calculation

Solution Overview

Problem

Current GPUs lack integer division logic in their arithmetic logic units, making it inefficient to perform memory address calculations for error correction, as standard integer division is slow and consumes excessive circuit space.

Innovation Solution

Implementing an error correction code (ECC) integrated circuit that subdivides memory addresses into coefficients for a polynomial equation, allowing for integer division-like operations through addition, enabling efficient address translation and checksum calculations without requiring additional circuit space for general integer division capabilities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If standard integer division logic is implemented in GPU arithmetic logic units, then address translation for error correction can be performed, but circuit space consumption increases and operation speed decreases

Engineering Contradiction:

Improveerror correction capabilityVSAvoidcircuit space

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the integer division operation into two separate calculations: quotient calculation using polynomial coefficients and remainder calculation using coefficient summation. This segmentation allows the GPU to perform address translation using only addition operations, avoiding the need for complex division logic while maintaining error correction capability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent replaces the mechanical integer division operation with a mathematical polynomial-based calculation system. By expressing memory addresses as polynomials and using coefficient operations, the system substitutes complex division mechanics with simpler addition-based calculations that can be performed efficiently on GPU hardware.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If standard integer division logic is implemented in GPU arithmetic logic units, then address translation for error correction can be performed, but operation speed decreases

Engineering Contradiction:

Improveerror correction capabilityVSAvoidaddress calculation speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The patent segments the integer division operation into two separate calculations: quotient calculation using polynomial coefficients and remainder calculation using coefficient summation. This segmentation allows the GPU to perform address translation using only addition operations, avoiding the need for complex division logic while maintaining error correction capability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent replaces the mechanical integer division operation with a mathematical polynomial-based calculation system. By expressing memory addresses as polynomials and using coefficient operations, the system substitutes complex division mechanics with simpler addition-based calculations that can be performed efficiently on GPU hardware.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Adaptability or versatility

If general integer division capabilities are added to GPU arithmetic logic units, then address translation is enabled, but hardware expense increases

Engineering Contradiction:

Improveaddress translation capabilityVSAvoidhardware expense

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent creates a universal polynomial-based calculation system that can handle address translation for error correction using only the GPU's existing addition capabilities. This multi-functional approach allows the same simple calculation logic to work for various address translation scenarios without requiring specialized division hardware.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent replaces the mechanical integer division operation with a mathematical polynomial-based calculation system. By expressing memory addresses as polynomials and using coefficient operations, the system substitutes complex division mechanics with simpler addition-based calculations that can be performed efficiently on GPU hardware.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS8370705B1System and method for calculating a checksum address while maintaining error correction information

Publication Date: 2013.02.05 NVIDIA CORP

AI summary

One or more embodiments of the invention set forth techniques to perform integer division using addition operations in order to provide address translation capabilities to a processor. The processor supports a memory that maintains checksum information such that address requests received by the processor need to be translated to a checksum address and an actual data address that accounts for use of portions of the memory to store checksum information. Once the checksum address and the actual data address are computed, the processor can confirm the integrity of the data stored in the actual data address and correct any errors if need be, based on the checksum information stored in the checksum address.