DRAM ECC Merging Logical-to-Physical Address Entries
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Solution Overview
Problem
Flash memory systems face challenges in conserving storage capacity while maintaining error-correcting capabilities, as conventional logical-to-physical address translation maps are inefficient due to large table sizes and inability to merge addresses effectively.
Innovation Solution
Implementing a logical-to-physical address translation map that merges multiple addresses into a single entry, encoded with an error-correcting code (ECC) to increase storage capacity and preserve error-correcting capabilities, where the ECC serves both error correction and address identification functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional logical-to-physical address translation maps are used, then error-correcting capabilities are maintained, but storage capacity is insufficient due to large table sizes and inability to merge addresses
Solution Approach 1:
The patent merges multiple address entries into a single mapping table entry, allowing multiple logical addresses to map to multiple physical locations through a consolidated structure. This merging reduces the overall number of entries in the translation map, decreasing memory requirements while maintaining the ability to address multiple physical locations through the merged entry
Solution Approach 2:
The error-correcting code (ECC) is designed to serve dual functions: traditional error detection and correction, plus address identification for multiple physical locations. By encoding the ECC to contain both error correction information and address data, the system eliminates the need for separate address storage, thereby increasing storage capacity while maintaining error correction capabilities
2Quantity of substance
If multiple addresses are merged into a single entry, then storage capacity increases, but error correction complexity increases
Solution Approach 1:
The ECC structure is designed to perform multiple functions simultaneously: error detection, error correction, and address identification. By embedding address information within the ECC words themselves, the system eliminates the need for separate address storage structures, thereby doubling the addressable space while managing complexity through unified encoding
Solution Approach 2:
The patent modifies the parameters of the ECC system by changing how ECC words are structured and interpreted. Instead of using ECC solely for error correction, the system repurposes portions of the ECC structure to encode address information, effectively changing the parameter space utilization to achieve doubled addressable capacity
Data Source
AI summary
The present disclosure generally relates to solid state storage device and techniques for conserving storage capacity associated therewith. Several embodiments are presented, including a data storage device, data storage controller, and methods for using the same are provided in the subject disclosure. A data storage device includes: a plurality of memory devices, a controller coupled to the plurality of memory devices and configured to program data to and read data from the plurality of memory devices, a memory including a logical-to-physical address translation map configured to enable the controller to determine a physical location of stored data in the plurality of memory devices, where the logical-to-physical address translation map contains at least one entry that merges at least two addresses that map, respectively, to at least two physical locations in the plurality of memory devices, where the controller is configured to encode each merged entry with an error-correcting code.