ECC Circuit Using Address and Sequence Checks for Memory Errors
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Solution Overview
Problem
Traditional error correction code (ECC) systems in computer memory systems are limited in detecting errors beyond data bits, failing to concurrently detect errors in multiple data words and other types of errors like address decoder or logic errors, which can lead to unpredictable behavior and longer bootup times due to spurious errors from uninitialized memory.
Innovation Solution
The ECC system generates codes based on both data bits and address and sequencing information, allowing detection of write and read address decoding errors, write enable failures, and stale data errors without requiring additional memory, using a single ECC generation circuit to support multiple memory lines and eliminating the need for initialization during bootup.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ECC systems are used to detect data errors, then data integrity is improved, but the system cannot detect address decoder errors or logic errors
Solution Approach 1:
The ECC system is enhanced to perform multiple functions: it not only detects data bit errors but also detects address decoder errors, logic errors, and write enable failures. The syndrome decoder is designed to analyze both data words and address bits, enabling a single system to handle multiple error types that traditional ECC systems could not detect simultaneously.
2Reliability
If additional memory is added to store ECC codes for address bits, then address error detection is improved, but hardware cost and power consumption increase
Solution Approach 1:
The patent combines the storage of data bits and address bits into a single memory structure, and combines the ECC protection for both into a unified ECC code. Instead of having separate memory resources for data ECC and address ECC, the system uses one integrated ECC generation and verification process that protects both data and address information, thereby reducing the total memory resources required.
Solution Approach 2:
The ECC code serves multiple purposes simultaneously: it protects data integrity and provides address error detection capability. This multi-functional ECC code eliminates the need for additional dedicated memory resources that would be required if separate ECC systems were implemented for address protection.
3Reliability
If memory is initialized at bootup to prevent spurious ECC errors, then error detection reliability is improved, but bootup time increases
Solution Approach 1:
The system performs preliminary validation by incorporating address bits into the ECC code generation process during store operations. This preliminary action ensures that when data is written, the associated address information is simultaneously protected by the ECC code. During read operations, the address bits are regenerated and verified against the stored ECC code, allowing the system to detect uninitialized memory conditions without requiring a separate initialization phase.
4Device complexity
If a single ECC generation circuit supports multiple memory lines, then device complexity is reduced, but the ability to concurrently detect errors in multiple data words is limited
Solution Approach 1:
The single ECC generation circuit is designed with multi-functional capability to handle multiple memory lines. The circuit can generate ECC codes that encompass information from multiple data words and their associated address bits, enabling concurrent error detection across multiple memory lines without requiring separate ECC circuits for each line.
Data Source
AI summary
Various embodiments include an error correction code (ECC) system that provides protection against various errors in addition to data bit errors. In general, ECC codes protect against data bit errors, where one or more data bits in a data word contain the wrong value. The ECC code is based on the original data bits, such that a data bit error results in a data word that is inconsistent with the ECC code generated for and stored with the data word. The present embodiments generate ECC codes based on address information and/or sequencing information in addition to the data bits in the data word. As a result, the present embodiments detect bit errors in this address information and/or sequencing information. Such errors include write address decoding errors, read address decoding errors, write enable errors, and stale data errors.