Memory Array Address Transformation for Uncorrectable ECC Errors
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Solution Overview
Problem
Semiconductor memories face challenges in reducing uncorrectable memory errors due to systemic errors caused by physical locations within memory arrays, which can overload error correction codewords, leading to uncorrectable errors.
Innovation Solution
The solution involves transforming addresses to distribute bits of a codeword across multiple memory arrays, using a control register to map physical addresses to logical array addresses, and applying transformations such as circular shifts or arithmetic operations to ensure unique array addresses, thereby reducing the impact of systemic errors and uncorrectable errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction codewords are used to protect memory data, then reliability is improved, but systemic errors at common physical locations can overload the error correction capacity leading to uncorrectable errors
Solution Approach 1:
The patent divides the codeword bits across multiple memory arrays instead of storing them contiguously. By segmenting the codeword and distributing its bits to different physical locations across multiple arrays, the patent prevents systemic errors at any single location from overwhelming the error correction capacity. This segmentation ensures that errors are spread out and remain within correctable limits.
Solution Approach 2:
The patent introduces a new dimension of organization by mapping codeword bits to multiple memory arrays along different address dimensions. Instead of linear storage within a single array, the codeword is distributed across arrays in a multi-dimensional address space, ensuring that systemic errors affecting one array or location do not concentrate on the entire codeword.
2Productivity
If memory arrays are densely packed in cross-point arrays, then productivity is improved, but common physical locations across arrays can cause systemic errors
Solution Approach 1:
The patent segments the codeword storage across multiple densely packed arrays, ensuring that even though the arrays are physically close and densely integrated, the actual data bits of any given codeword are separated across different arrays. This maintains high density while preventing systemic errors from affecting the entire codeword.
Solution Approach 2:
The patent applies local quality by assigning different mapping patterns to different codewords or different portions of the address space. This ensures that locally dense arrays contribute to global error distribution, where each local array serves a specific role in the overall error correction strategy.
3Device complexity
If physical addresses are directly mapped to array locations, then device complexity is reduced, but uncorrectable errors increase due to systemic defects
Solution Approach 1:
The patent performs preliminary address transformation during the address mapping process. Before accessing the memory arrays, the controller transforms the logical address to a physical address using a function that distributes codeword bits across arrays. This preliminary action embeds the error distribution strategy into the address mapping itself, maintaining simplicity while achieving reliability.
Solution Approach 2:
The patent introduces an address transformation function as an intermediary between the logical address space and the physical array locations. This intermediary layer implements the distribution logic without requiring complex hardware reconfiguration, using a mathematical function to map addresses in a way that automatically achieves error distribution.
Data Source
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AI summary
Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.