ECC Bit-Flipping Correction for Multi-Bit Memory Errors
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Solution Overview
Problem
Current ECC-based data storage systems face increased complexity and longer processing times due to aggressive scaling in semiconductor technology, leading to higher bit error rates and power consumption, as well as longer propagation delays.
Innovation Solution
The implementation of simplified ECC-based systems and methods that reduce the complexity of logic circuitry for bit error detection and correction, using techniques like bit flipping to quickly and accurately detect and correct single and multi-bit errors, thereby reducing integrated circuit layout area, power consumption, and processing times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If current ECC-based systems are used with aggressive scaling, then data storage capacity increases, but logic circuitry complexity and processing time increase
Solution Approach 1:
The patent segments the error correction process into distinct modules: syndrome calculation unit, error detection unit, and error correction unit. Each module handles specific tasks independently, reducing overall circuit complexity while maintaining comprehensive error correction capability for both single-bit and multi-bit errors
Solution Approach 2:
The patent implements selective error correction by first detecting single-bit errors and only proceeding to multi-bit error correction when necessary. This partial action approach reduces average processing time and circuit complexity by avoiding full multi-bit correction procedures for all data cases
2Quantity of substance
If current ECC-based systems are used with aggressive scaling, then data storage capacity increases, but processing time increases
Solution Approach 1:
The patent performs preliminary syndrome calculation and error detection before full correction procedures. By pre-calculating syndromes and detecting error types early in the process, the system avoids unnecessary complex correction operations, significantly reducing average processing time while maintaining high storage capacity
Solution Approach 2:
The error correction process is divided into time-segmented stages: syndrome calculation, single-bit error detection and correction, and multi-bit error correction. This segmentation allows the system to complete simpler operations first and only proceed to time-consuming multi-bit correction when absolutely necessary
3Quantity of substance
If current ECC-based systems are used with aggressive scaling, then data storage capacity increases, but power consumption increases
Solution Approach 1:
The patent implements power-efficient partial correction by detecting single-bit errors and correcting them using low-power operations, only activating the more power-intensive multi-bit error correction circuitry when actually needed. This selective approach significantly reduces average power consumption while maintaining high storage capacity
Solution Approach 2:
The power consumption is segmented into different operational modes corresponding to different error types. Single-bit error handling uses a simplified, low-power circuit path, while multi-bit error correction uses the full correction capability only when required, optimizing the balance between storage capacity and power usage
Data Source
AI summary
A method of correcting one or more bit errors in a memory device includes retrieving a codeword from a memory device. The codeword includes a data and an error correcting code. The method further includes determining whether the one or more bit errors are present in the retrieved codeword and correcting the retrieved codeword for the one bit error in response to determining one bit error is present in the retrieved codeword. The method also includes flipping a bit of the retrieved codeword in response to determining a plurality of bit errors is present in the retrieved codeword and correcting the retrieved codeword for the plurality of bit errors based on the bit-flipped codeword.