Error Correction Code Buffering for Low-Latency PO Encoding
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Solution Overview
Problem
Conventional error correction code generation in data storage systems, such as DVDs and HD-DVDs, experiences poor DRAM access efficiency due to frequent page-crossing access during PO encoding, leading to increased latency and reduced performance.
Innovation Solution
An error correction code generator architecture that includes a buffer and an operating device to store and process data in a way that minimizes page misses by accessing data along the row direction, using recursive remainder polynomials and XOR logical operations to generate error correction codes efficiently, potentially utilizing two-port or single-port SRAMs to reduce buffer size and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scrambled source data are sequentially read out from DRAM column by column for generating PO codes, then error correction codes can be generated, but frequent page-crossing access occurs resulting in poor DRAM access efficiency
Solution Approach 1:
The patent inverts the conventional column-by-column read approach to row-by-row read approach. Instead of reading data column by column from DRAM, the system reads data row by row, fundamentally changing the access pattern to eliminate frequent page-crossing operations and improve DRAM access efficiency while still generating the required PO codes for error correction
2Reliability
If conventional PO encoding process is used with column-by-column data access, then error correction codes are generated, but access latency increases due to frequent page misses
Solution Approach 1:
The patent inverts the conventional column-by-column read approach to row-by-row read approach. Instead of reading data column by column from DRAM, the system reads data row by row, fundamentally changing the access pattern to eliminate frequent page-crossing operations and improve DRAM access efficiency while still generating the required PO codes for error correction
3Productivity
If additional data buffers are added to improve encoding performance, then processing capacity increases, but hardware cost and device complexity increase
Solution Approach 1:
The patent makes the existing buffer serve multiple functions: it stores both the input data to be encoded and the generated PO codes simultaneously. By optimizing the buffer's data structure and access patterns, the system eliminates the need for separate dedicated buffers for different stages of the encoding process, thereby reducing overall hardware requirements while maintaining encoding performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves PO encoding performance by reducing the need for additional data buffers, decreasing latency, and enhancing overall encoding efficiency, allowing for concurrent data processing and reduced hardware costs.
Implementation Method 1
an operating device coupled to the buffer for generating operating results according to the calculating data from the buffer and corresponding data of the data block
Implementation Method 2
The generation of the PO codes within the PO block 120 can be described by the following remainder polynomial Rj(X):
Data Source
AI summary
Methods and apparatuses for generating error correction codes of a data block are disclosed. One proposed method includes: storing a plurality of calculating data corresponding to the error correction codes in a buffer; generating operating results according to the calculating data from the buffer and corresponding data of the data block; writing operating results into the buffer; and generating a plurality of updated calculating data according to the operating results stored in the buffer.