ECC Cache for Automotive Memory Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The high cost and complexity of implementing error correction code (ECC) in DDR DRAM memory, particularly in automotive systems, where non-standard memory sizes and interfaces are required, lead to increased costs and inefficiencies, such as doubling the overhead due to self-refresh operations and the need for additional memory devices.
Innovation Solution
Implementing an ECC cache on the System on Chip (SoC) and using data compression to store ECC bits with compressed data in a single memory device, allowing for ECC implementation in a single 2x16b piece of memory and a 32b memory access channel, compliant with ASIL-A through ASIL-D standards, thereby reducing the need for additional memory and access channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory is used to meet automotive safety standards with ECC, then reliability is improved, but device complexity and cost increase
Solution Approach 1:
The patent combines ECC functionality with a cache memory structure, creating an ECC cache that performs both error correction and caching operations within a single memory system. This merging eliminates the need for separate ECC hardware and reduces the number of memory devices required, directly addressing the complexity and cost issues while maintaining reliability
2Adaptability or versatility
If custom-designed DDR DRAM memory is implemented to meet specific product requirements, then adaptability is improved, but manufacturing cost increases
Solution Approach 1:
The ECC cache design provides multiple functions within a single memory structure: it serves as both an error correction mechanism and a cache memory, while also supporting different memory configurations and access patterns. This multi-functionality allows the system to adapt to various automotive safety standards (ASIL-A through ASIL-D) without requiring custom-designed memory for each application, reducing manufacturing costs
3Reliability
If additional memory devices are added to implement ECC, then reliability is improved, but loss of substance increases
Solution Approach 1:
The patent implements ECC functionality nested within the cache memory structure, where ECC bits are stored and processed within the same memory hierarchy as the data. This nesting approach allows error correction to be performed using the existing memory infrastructure without requiring additional standalone memory devices, thereby reducing memory overhead while maintaining data protection
4Reliability
If memory access channel width is increased to support ECC, then reliability is improved, but use of energy increases
Solution Approach 1:
By merging ECC operations with cache memory operations, the system performs error correction using the same access channels and memory infrastructure already required for data access. This eliminates the need for separate wide access channels dedicated to ECC, reducing energy consumption while maintaining error correction capability
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
Systems and methods are disclosed for error correction control (ECC) for a memory device comprising a data portion and an ECC portion, the memory device coupled to a system on a chip (SoC). The SoC includes an ECC cache. On receipt of a request to write a line of data to the memory, a determination is made if the data is compressible. If so, the data line is compressed. ECC bits are generated for the compressed or uncompressed data line. A determination is made if an ECC cache line is associated with the received data line. If the data line is compressible, the ECC bits are appended to the compressed data line and the appended data line is stored in the data portion of the memory. Otherwise, the ECC bits are stored in the ECC cache and the data line is stored in the data portion of the memory.