Pipelined ECC Cache Access Speculative Execution
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Solution Overview
Problem
As transistor geometries shrink, increasing the likelihood of soft errors in caches, existing error detection and correction techniques in semiconductor memories become more costly and inefficient, particularly in pipelined processing systems where error correction prolongs cache access times.
Innovation Solution
Implementing a pipelined Error Correction Code (ECC) cache access method that allows speculative execution and operates in multiple modes, enabling concurrent processing of transactions while correcting errors, and switching to error mode only when necessary to avoid conflicts and maintain throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC calculation and correction process is performed for each cache transaction, then error detection and correction capability is improved, but cache access time is prolonged
Solution Approach 1:
The patent performs ECC calculation and correction in advance during pipeline stages before the cache access is actually needed. By initiating ECC processing early in the pipeline for current transactions while speculative compares are performed, the system ensures error correction is completed before results are needed, eliminating delays in the critical path.
Solution Approach 2:
The patent dynamically adjusts pipeline behavior based on error detection results. When errors are detected, the pipeline transitions to error mode where speculative compares are disabled and ECC-corrected tags are used. When no errors are detected, the pipeline operates in normal mode with full speculative execution, optimizing throughput for the majority of error-free transactions.
2Speed
If speculative tag compare and data RAM read are performed concurrently with ECC process, then transaction processing speed is improved, but pipeline complexity increases
Solution Approach 1:
The patent segments the cache access pipeline into distinct functional stages: tag reading with ECC calculation, speculative tag compare, ECC correction, and data retrieval. Each stage operates independently with clearly defined inputs and outputs, allowing concurrent execution of ECC processes and speculative compares while maintaining manageable complexity through modular design.
Solution Approach 2:
The patent introduces intermediate buffers and control signals to manage the interaction between speculative execution units and ECC correction units. These intermediaries coordinate data flow between parallel pipeline stages, ensuring that ECC-corrected tags are properly selected and that speculative operations are conditionally enabled or disabled based on error detection results.
3Reliability
If error mode is entered after detecting correctable error, then data accuracy is improved, but subsequent transaction processing is delayed
Solution Approach 1:
The patent changes the operational parameters of the pipeline based on error detection. In normal mode (no errors), the pipeline enables speculative compares and operates with shorter latency. In error mode (correctable errors detected), the pipeline disables speculative compares and uses ECC-corrected tags, ensuring data accuracy while accepting increased latency for affected transactions.
Solution Approach 2:
The patent periodically checks for errors in batches of transactions and adjusts pipeline mode accordingly. Rather than processing each transaction individually with full error checking, the system processes transactions in pipelines, detecting errors periodically at stage boundaries, and switching modes only when necessary, thereby maintaining high throughput for error-free transaction sequences.
Data Source
AI summary
In one aspect, a pipelined ECC-protected cache access method and apparatus provides that during a normal operating mode, for a given cache transaction, a tag comparison action and a data RAM read are performed speculatively in a time during which an ECC calculation occurs. If a correctable error occurs, the tag comparison action and data RAM are repeated and an error mode is entered. Subsequent transactions are processed by performing the ECC calculation, without concurrent speculative actions, and a tag comparison and read are performed using only the tag data available after the ECC calculation. A reset to normal mode is effected by detecting a gap between transactions that is sufficient to avoid a conflict for use of tag comparison circuitry for an earlier transaction having a repeated tag comparison and a later transaction having a speculative tag comparison.