Dynamic Memory ECC Caching for Write Throughput
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Advanced driver assistance systems (ADAS) and autonomous vehicle (AV) systems face challenges in efficiently managing and correcting errors in memory, particularly when transitioning to fully autonomous operations.
Innovation Solution
The method involves opening a selected row of a dynamic memory module, receiving data sub-blocks, calculating error correction code sub-blocks, caching these codes in a separate cache memory, and writing them to the dynamic memory module while the row is open, triggered by the need to clean the dynamic memory controller state before entering low power modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction codes are calculated and written to dynamic memory module, then data reliability is improved, but write throughput is reduced due to additional processing time
Solution Approach 1:
The error correction code is calculated preliminarily while the row is open and data is being received, before the actual write operation to the dynamic memory module. This preliminary calculation of ECC sub-blocks does not block the data write path, allowing data to be written while ECC is being prepared, thus maintaining high write throughput while ensuring data reliability through error correction coding.
2Reliability
If error correction codes are written to dynamic memory module, then data reliability is improved, but the penalty for error correction increases due to additional write operations
Solution Approach 1:
The error correction code write operation is merged with the data write operation by both being written to the same open row in the dynamic memory module. This combining of data and ECC writes into a single memory transaction eliminates the need for separate write operations, thereby reducing the time penalty associated with error correction while maintaining improved data reliability.
3Device complexity
If a separate cache memory is used for error correction codes, then device complexity is reduced, but access time increases due to additional memory access
Solution Approach 1:
The memory system is segmented into dynamic memory module for data storage and a separate cache memory for error correction codes. This segmentation allows each memory component to be optimized independently - the cache memory can be smaller and faster for ECC storage while the dynamic memory module handles bulk data, reducing overall device complexity while managing access time through intelligent caching strategies.
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
A method for error correction and a system. The method may include opening a selected row of a memory bank out of multiple memory banks of a dynamic memory module; and while the selected row is open : (i) receiving selected data sub-blocks that are targeted to be written to the selected row, (ii) calculating selected error correction code sub-blocks that are related to the selected data sub-blocks, (iii) caching the selected error correction code sub-blocks in a cache memory that differs from the dynamic memory module and (iv) writing, to the selected row, the selected error correction code sub-blocks.