ECC Check Matrix Odd-Even Weight Distribution for Memory Error Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing complexity of semiconductor memory systems makes it difficult to fabricate defect-free memory cells, leading to errors during data transmission and storage, which existing error correction methods struggle to address effectively, often resulting in mis-correction and increased errors.
Innovation Solution
A memory system utilizing an ECC generation circuit that generates an M-bit error correction code using an M×(N+M) check matrix, where one column vector has an odd weight and the others have even weights, to correct errors in N-bit data, thereby reducing mis-correction and stabilizing the memory system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC circuits are used to correct errors in memory systems, then error correction capability is provided, but mis-correction occurs and errors increase
Solution Approach 1:
The patent changes the weight distribution parameter of column vectors in the check matrix from conventional uniform or random weights to a specific pattern where exactly one column vector has odd weight and all others have even weights. This parameter change fundamentally alters the error correction behavior to prevent mis-correction while maintaining error correction capability.
Solution Approach 2:
The patent introduces asymmetry in the check matrix structure by having one unique column vector with odd weight while all other column vectors have even weights. This asymmetric design creates a distinctive signature that allows the ECC circuit to identify and avoid mis-correction scenarios, resolving the contradiction between providing error correction and preventing error escalation.
2Quantity of substance
If memory capacity is increased to meet growing storage demands, then storage capability is improved, but the probability of defective cells increases to almost zero
Solution Approach 1:
The patent applies preliminary error correction by generating ECC codes using the specialized check matrix before data is stored in memory. This preliminary action prepares the data with built-in error detection and correction capabilities, allowing the system to handle defective cells that inevitably occur in high-capacity memories without compromising reliability.
3Reliability
If existing ECC methods are used to handle errors in high-capacity memories, then error correction is attempted, but mis-correction occurs leading to increased errors
Solution Approach 1:
The patent implements a feedback mechanism where the ECC circuit uses the weight pattern information from the check matrix to verify whether correction is appropriate before performing error correction. This feedback loop prevents mis-correction by checking whether the error pattern matches valid correction criteria, thereby maintaining data integrity while handling errors in high-capacity memories.
Data Source
AI summary
A memory system may include: an error correction code (ECC) generation circuit suitable for generating an M-bit error correction code using N-bit data, where N and M are positive integers; a memory core suitable for storing the N-bit data and the M-bit error correction code; and an ECC circuit suitable for correcting an error of the N-bit data read from the memory core, using the M-bit error correction code read from the memory core, wherein the ECC generation circuit generates the M-bit error correction code using an M×(N+M) check matrix, wherein one column vector among M column vectors corresponding to the M-bit error correction code in the M×(N+M) check matrix has an odd weight, and the other M column vectors have even weights.