Selective ECC Checkbit Inversion for Memory Error Detection
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Solution Overview
Problem
Conventional error detection and correction systems in data processing devices struggle to differentiate between valid and invalid data transfers due to the generation of undesired codewords, particularly when errors occur in memory addresses, leading to potential misdetection of errors.
Innovation Solution
The implementation of an end-to-end error detection and correction scheme that selectively inverts ECC checkbits based on specific memory addresses to avoid the generation of undesired codewords, ensuring accurate error detection and correction by incorporating address information into the checkbit calculation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC checkbits are generated for data storage, then error detection and correction capability is improved, but misdetection of errors occurs due to undesired codeword generation from memory address errors
Solution Approach 1:
The patent inverts the conventional approach by incorporating memory address information into the ECC checkbit generation process. Instead of generating checkbits solely from data, the system generates checkbits that are functions of both data and address, thereby enabling the detection of address-related errors that would otherwise produce undesired codewords.
Solution Approach 2:
The patent introduces address information as an intermediary element in the checkbit generation process. This intermediary connects the memory address to the error correction mechanism, allowing the system to detect errors in both data and address through the same ECC checkbits.
2Reliability
If ECC checkbits are used for error correction, then data integrity is improved, but the system cannot differentiate between valid and invalid data transfers due to undesired codewords
Solution Approach 1:
The patent inverts the conventional approach by incorporating memory address information into the ECC checkbit generation process. Instead of generating checkbits solely from data, the system generates checkbits that are functions of both data and address, thereby enabling the detection of address-related errors that would otherwise produce undesired codewords.
Solution Approach 2:
The patent applies local quality by making the checkbit generation process address-specific. Different memory addresses generate different checkbit patterns for the same data, creating localized error detection capabilities that are tailored to each address location and enable differentiation between valid and invalid transfers.
3Reliability
If end-to-end error detection is implemented, then error detection coverage is improved, but complexity of the error detection system increases
Solution Approach 1:
The patent merges the error detection for data and address into a single unified ECC checkbit generation process. By combining address information with data in the checkbit calculation, the system achieves end-to-end error detection coverage without requiring separate detection mechanisms, thereby limiting the increase in system complexity.
Data Source
AI summary
Error correction code (ECC) checkbits are generated for each write access to a memory address based on both the data to be written (the write data) and the memory address. The ECC checkbits are stored with the data and, in response to a read access at the memory address, are employed to check for errors in both the address and the data provided in response to the read access (the read data). The ECC checkbit generation process can result, for particular memory addresses, in checkbits that can incorrectly indicate whether errors are present in the read data. Accordingly, the checkbits can be selectively inverted based on the memory address so that the checkbit pattern will not result in an incorrect error detection or correction.