ECC Circuitry Checker for Memory Error Detection Validation

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Solution Overview

Problem

In embedded computing systems, particularly those requiring high safety levels such as automotive applications, there is a need to verify the correct operation of error detection mechanisms to ensure they are functioning as intended, as defective error detection circuitry may not detect errors it is designed to identify.

Innovation Solution

Incorporating ECC circuitry checkers that substitute ECC data with check data, compare outputs to expected results, and generate alerts for errors, thereby validating the operation of ECC circuitry in memory and bus interfaces within the system.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error detection circuitry is implemented in embedded systems, then reliability is improved, but the ability to detect defects in the error detection circuitry itself deteriorates

Engineering Contradiction:

Improveerror detection capabilityVSAvoiddefect detection in error detection circuitry

Core Design Contradiction:

ReliabilityVSDifficulty of detecting and measuring

Solution Approach 1:

The patent introduces a test mode operation that acts as an intermediary mechanism. In this mode, the control logic forces specific data patterns and error conditions through the error detection circuitry, allowing indirect verification of the circuitry's functionality without requiring direct observation of its internal operations.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements preliminary testing by forcing known error patterns and data values through the error detection circuitry before normal operation. This preliminary action allows the system to verify that the error detection logic functions correctly under controlled conditions, establishing a baseline for detecting defects.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If comprehensive error detection is implemented, then safety is improved, but system complexity increases

Engineering Contradiction:

Improvesafety levelVSAvoidverification mechanism complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The error detection circuitry performs self-verification by comparing its own output against expected results generated from forced input patterns. The control logic monitors the error detection circuitry's behavior and generates alerts when discrepancies occur, enabling the system to self-diagnose without external intervention.

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The patent implements feedback mechanisms where the output of the error detection circuitry is continuously monitored and compared against expected values. When the actual output deviates from the expected output, the control logic generates an alert, creating a closed-loop feedback system that automatically detects and reports defects.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS11940872B2Error correction code validation

Publication Date: 2024.03.26 ANALOG DEVICES INT UNLTD CO

AI summary

A memory device comprising a memory array including memory cells to store memory data, error correcting code (ECC) circuitry configured to generate ECC data and use the ECC data to detect errors in the memory data, and an ECC circuitry checker. The ECC circuitry checker is configured to substitute the ECC data with check ECC data, compare an output of the ECC circuitry to an expected output when the substituted check ECC data is applied to the ECC circuitry, and generate an alert when the comparing indicates an error in the ECC circuitry.