Memory Controller ECC Chunk Segmentation for QLC Flash Reliability
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Solution Overview
Problem
Existing memory devices with multi-level cell flash memories, such as QLC, face issues like increased bit error rates and degraded system reliability due to the weakest page, which traditional sensing schemes cannot effectively address.
Innovation Solution
A method involving a memory controller that generates error correction code (ECC) chunks and maps them one-to-one with sets of memory cells to prevent sharing, enhancing read performance and system reliability without significant additional cost or side effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional sensing schemes are used for reading data from TLC/QLC flash memories, then the system can operate with existing architecture, but the bit error rate increases and system reliability degrades due to the weakest page
Solution Approach 1:
The patent segments ECC chunks and memory cells into corresponding groups, establishing one-to-one mapping relationships. Each ECC chunk is assigned to a specific memory cell group, allowing independent error correction for each segment. This segmentation prevents the weakest page from limiting overall system reliability while maintaining manageable complexity through structured organization.
Solution Approach 2:
The patent performs preliminary arrangement of ECC chunks and memory cells before actual data access operations. By pre-establishing the one-to-one mapping between ECC chunks and memory cell groups during the write operation, the system prepares the error correction structure in advance, eliminating the need for complex real-time sensing schemes and improving reliability from the outset.
2Productivity
If multiple ECC chunks share the same set of memory cells, then storage capacity is maximized, but read performance degrades due to access conflicts and error propagation
Solution Approach 1:
The patent divides the storage system into independent segments where each ECC chunk corresponds to a dedicated memory cell group. This segmentation eliminates access conflicts between ECC chunks during read operations, as each chunk can be independently decoded without waiting for other chunks. The one-to-one mapping ensures that error correction for one chunk does not interfere with others, maintaining high read performance while preserving storage capacity through efficient space utilization.
3Quantity of substance
If QLC flash memories are used to increase storage density, then capacity increases, but bit error rate increases and system reliability decreases
Solution Approach 1:
The patent applies segmentation by creating independent error correction units where each ECC chunk is mapped to a specific memory cell group in the QLC flash memory. This allows targeted error correction for each segment without being affected by errors in other segments. The one-to-one mapping ensures that the high bit error rate characteristic of QLC memories does not propagate system-wide, as each ECC chunk can be independently decoded and corrected, thereby maintaining system reliability while utilizing the high storage capacity of QLC technology.
Data Source
AI summary
A method for performing access management of a memory device with aid of information arrangement and associated apparatus (e.g. the memory device and controller thereof, and an associated electronic device) are provided. The method may include: when the host device sends a write command to the memory device, utilizing the memory controller to generate a plurality of ECC chunks respectively corresponding to a plurality of sets of memory cells of the NV memory according to data, for establishing one-to-one mapping between the plurality of ECC chunks and the plurality of sets of memory cells; and utilizing the memory controller to store the plurality of ECC chunks into the plurality of sets of memory cells, respectively, to prevent any two ECC chunks of the ECC chunks from sharing a same set of memory cells of the sets of memory cells, to enhance read performance of the memory controller regarding the data.