Memory Controller ECC Circuit Parallel Decoding for Read Latency
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Solution Overview
Problem
Resistive memory devices face reliability issues due to varying resistance distributions over time, leading to reduced read data reliability and increased latency in detecting optimal read levels.
Innovation Solution
A memory controller with an error correction code (ECC) circuit that generates change codewords by altering bit values of read codewords and performs parallel ECC decoding to correct errors, reducing the need for multiple read operations and minimizing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple read operations are performed to detect optimal read level, then read data reliability is improved, but latency increases
Solution Approach 1:
The patent performs ECC decoding in advance on multiple candidate codewords (including original and modified versions) before final data selection. By pre-processing and preparing multiple potential correct codewords through parallel ECC decoding, the system eliminates the need for iterative read operations to detect optimal read levels, thereby reducing latency while maintaining high reliability
Solution Approach 2:
The system dynamically modifies codeword bits to generate multiple candidate codewords from a single read operation. By dynamically altering bit values in the codeword and generating multiple variations, the system enables parallel ECC decoding to handle different scenarios, achieving both improved reliability and reduced latency without requiring multiple sequential reads
2Reliability
If ECC decoding is performed on multiple codewords, then error correction possibility is enhanced, but processing complexity increases
Solution Approach 1:
The patent segments the ECC decoding process into multiple independent parallel operations, where each ECC engine handles a specific candidate codeword simultaneously. This segmentation allows the system to enhance error correction capability by checking multiple codewords without proportionally increasing overall processing complexity, as each segment operates independently and concurrently
Solution Approach 2:
The system changes parameters of the codeword (specifically bit values) to generate multiple candidate versions. By systematically varying bit parameters in the original codeword to create modified codewords, the patent enables comprehensive error correction coverage while maintaining manageable processing complexity through structured parameter variation rather than exhaustive search
3Reliability
If bit values of read codeword are modified to generate change codeword, then error correction capability is improved, but device complexity increases
Solution Approach 1:
The patent performs preliminary modification of codeword bits to generate candidate codewords before ECC decoding. By pre-generating modified codewords with altered bit values, the system prepares multiple potential correct versions in advance, enhancing error correction capability while avoiding the need for complex iterative modification and re-decoding processes
Solution Approach 2:
The system creates copies of the original codeword with modified bit values to generate candidate codewords. Instead of directly manipulating the original data through complex transformations, the patent uses copying and selective bit flipping to generate variations, simplifying the overall device complexity while maintaining enhanced error correction capability
Data Source
AI summary
A memory controller is provided. The memory controller includes an error correction code (ECC) circuit configured to correct an error of a read codeword provided from a memory device, the ECC circuit including: a codeword combination generator configured to receive a first read codeword including a plurality of first read codeword bit values that are read from a first region of the memory device, generate a change codeword by changing values of one or more of the plurality of first read codeword bit values, and provide a codeword combination including the change codeword; and an ECC decoder including a plurality of ECC engines, wherein the ECC decoder is configured to perform ECC decoding in parallel on a plurality of codewords included in the codeword combination.