ECC Circuit Self-Testing Using Syndrome-Based Test Sequences
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Solution Overview
Problem
In integrated circuits, errors can lead to false corrections and unnecessary system-level measures due to miniaturization and low voltage/current values, and existing error detection methods require significant hardware and computational resources.
Innovation Solution
A device comprising a syndrome determiner, a test sequence provider, and an evaluation circuit that generates a test bit sequence different from the error syndrome bit sequence, allowing for error-free operation without additional computational time or hardware, by utilizing a modified parity check matrix to differentiate between code words and non-code words.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection is enhanced by adding redundancy in electronic circuits, then error detection probability increases, but hardware outlay increases
Solution Approach 1:
The syndrome determiner is designed to perform dual functions: determining error syndromes for error correction and generating test bit sequences for circuit testing. This multi-functionality allows the same hardware component to serve both error correction and testing purposes, thereby increasing error detection capability without proportionally increasing hardware outlay
Solution Approach 2:
The circuit uses its own operational periods (when no error correction is needed) to perform self-testing. The test sequence provider utilizes time slots where the coded binary word is already in correct form to automatically test the circuit, eliminating the need for separate dedicated testing hardware and reducing overall system complexity
2Reliability
If testing is performed frequently to detect errors, then error detection capability improves, but computational time increases
Solution Approach 1:
Testing is performed periodically during operational periods when the circuit is not engaged in error correction. The test sequence provider generates test bit sequences at specific time intervals (when syndrome indicates no error), allowing frequent testing without continuous computational overhead and maintaining high error detection capability while minimizing time loss
Solution Approach 2:
The testing operation is integrated into the normal operational flow of the circuit. Instead of interrupting computation for separate testing, the system continuously performs both error correction and testing functions by utilizing different time slots within the same operational framework, thereby maintaining continuous useful action without additional time penalty
Data Source
AI summary
A device for testing a circuit includes a syndrome determiner, a test sequence provider and an evaluation circuit. The syndrome determiner determines an error syndrome bit sequence (s(v′)) based on a coded binary word (v′). The error syndrome bit sequence (s(v′)) indicates whether the coded binary word (v′) is a code word of an error correction code (C) used for coding the coded binary word (v′). The test sequence provider provides a test bit sequence (Ti) of the circuit that is different than the error syndrome bit sequence (s(v′)), if the error syndrome bit sequence (s(v′)) indicates that the coded binary word (v′) is a code word of the error correction code (C). The evaluation circuit detects an erroneous processing of the test bit sequence (Ti) by the circuit based on a test output signal (R(Ti)′)—caused by the test bit sequence (Ti)—of the circuit.