ECC Clock Path Testing Using On-Chip Check Bit Generation
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Solution Overview
Problem
Testing integrated circuits with error checking and correcting (ECC) protected logic is challenging due to the difficulty in generating correct ECC check bit patterns during random pattern testing, as ECC codes increase code space and often result in incorrect check bits, making thorough testing inefficient.
Innovation Solution
Implementing a method that uses on-chip circuitry to generate correct ECC check bits by initializing a scan with correct ECC check bits and applying a global control bit to latches, allowing the ECC generation logic to create initialization values, thereby testing the ECC parity logic effectively and downstream logic in a system-like manner.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If random pattern testing is used to test ECC protected logic, then testing coverage can be achieved, but the probability of exercising correct ECC check bit patterns is extremely low
Solution Approach 1:
The patent applies preliminary action by pre-loading correct ECC check bit patterns into the scan chains before testing begins. The LBIST engine pre-generates and loads valid ECC patterns (such as all zeros, all ones, and specific error patterns) into the scan chains, ensuring that when testing starts, the correct patterns are already in place. This eliminates the need to rely on random pattern generation during testing, directly resolving the contradiction by guaranteeing high probability of exercising correct ECC patterns while maintaining comprehensive testing coverage.
2Productivity
If LBIST is used to test all random logic including ECC logic, then testing efficiency is improved, but the ability to generate correct ECC check bit patterns is insufficient
Solution Approach 1:
The patent introduces an intermediary mechanism - a dedicated control logic unit that works in conjunction with the LBIST engine. This control logic monitors the testing process and selectively loads correct ECC check bit patterns into the scan chains based on the test requirements. It acts as a mediator between the random pattern generation capability of LBIST and the need for precise ECC patterns, combining the efficiency of LBIST with the accuracy of predetermined ECC patterns.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the pattern generation parameters of the LBIST engine. When ECC logic testing is detected, the system changes the pattern generation parameters to produce valid ECC check bit patterns instead of purely random patterns. This parameter switching allows the same LBIST infrastructure to efficiently generate both random patterns for general logic testing and precise ECC patterns for encoded logic testing, resolving the contradiction between efficiency and accuracy.
Data Source
AI summary
Aspects include techniques for implementing a clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry for encoding and correction of a chip. A computer-implemented method may include initializing a scan of the chip including data and a set of check bits protecting the data; applying a global control bit to a latch on the chip; and applying an additional clock to the latch so the check bits are updated using the on-chip circuitry.