Non-Volatile Memory ECC Codeword Distribution Across Rows
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Solution Overview
Problem
Current data storage systems face limitations in capacity and efficiency due to the imbalance between system memory and storage drive capacities, leading to frequent page swapping and high write amplification, especially with new-generation high-error-rate and low-endurance memory media like ReRAM, PCM, and MRAM.
Innovation Solution
A system and method that uses a combination of aligned and misaligned mapping with error correction codes (ECC) to efficiently write and read data across multiple rows in non-volatile memory, reducing write amplification and internal data copy operations, and employing a controller for address mapping and error correction to handle high error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM capacity is increased to serve performance-critical applications, then system memory capacity is improved, but current DRAM technology limits capacity to 256GB maximum
Solution Approach 1:
The patent segments the ECC codeword into multiple parts distributed across different memory rows, allowing the memory system to scale beyond single-row limitations. This segmentation enables the use of high-density media with larger capacities while maintaining error correction capabilities across distributed data segments.
Solution Approach 2:
The patent transitions from traditional single-row memory organization to a multi-row distributed organization. By placing ECC codeword parts across multiple rows and using a mapping table to track their locations, the system effectively adds a dimensional aspect to memory addressing and management, enabling scalability to higher capacities.
2Quantity of substance
If page swapping between system memory and storage drive is increased to handle limited memory capacity, then memory capacity limitation is addressed, but processing speed decreases and system performance is reduced
Solution Approach 1:
The patent implements a memory system that effectively creates a large-capacity memory space by using high-density non-volatile media with capacities up to 4TB. The mapping table and distributed row structure allow the system to access this expanded memory space directly, reducing the need for frequent page swapping and improving processing speed while maintaining high capacity.
3Quantity of substance
If new-generation high-density memory media is used to increase storage capacity, then memory density is improved, but error rate increases and media endurance decreases
Solution Approach 1:
The patent applies error correction codes (ECC) to encode data before writing it to the high-density memory media. By pre-encoding the data with ECC capabilities and distributing the codeword parts across multiple rows, the system proactively prepares for potential errors, enabling error detection and correction when data is read back, thus maintaining data accuracy despite the high error rates of new-generation media.
4Reliability
If traditional ECC encoding is applied to high-density media, then error correction capability is improved, but write amplification increases
Solution Approach 1:
The patent distributes different parts of the ECC codeword across multiple memory rows, with each row containing a specific segment. This local organization allows the system to manage writes more efficiently by targeting specific rows rather than requiring full codeword rewrites, thereby reducing write amplification while maintaining comprehensive error correction capability across the entire data set.
Data Source
AI summary
The system receives a request to write a first piece of data to a non-volatile memory. The system encodes, based on an error correction code (ECC), the first piece of data to obtain a first ECC codeword which includes a plurality of ordered parts and a first parity. The system writes the plurality of ordered parts in multiple rows. The system writes the first parity to a same row in which a starting ordered part is written. The system updates, in a data structure, entries associated with the ordered parts. A respective entry indicates: a virtual address associated with a respective ordered part, a physical address at which the respective ordered part is written, and an index corresponding to a virtual address associated with a next ordered part. A first entry associated with the starting ordered part further indicates a physical address at which the first parity is written.