ECC Memory Codeword Scrambling for Parity Bit Endurance

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Conventional error correction code (ECC) non-volatile memory devices experience endurance failure due to excessive cycling of parity bits, which outlasts message bits, leading to performance degradation.

Innovation Solution

The proposed solution involves generating parity information based on an error correction algorithm for M message bits and transforming it into a scrambled codeword with N bits, where N > M, to reduce parity bit cycling and enhance ECC memory device performance by using a scrambling operation during data writing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If parity bits are generated and stored separately from message bits in conventional ECC memory, then error correction capability is maintained, but parity bits cycle much more frequently than message bits causing endurance failure

Engineering Contradiction:

Improveerror correction capabilityVSAvoidendurance

Core Design Contradiction:

ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The patent merges message bits and parity bits into a unified codeword structure before scrambling. By combining these bits and applying a single scrambling operation to the entire codeword, the invention ensures that message bits and parity bits switch in synchronization, preventing the excessive cycling of parity bits that causes endurance failure while maintaining error correction capability.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces dynamic scrambling operations that adaptively control the switching behavior of codeword bits. By applying scrambling before writing and descrambling before reading, the system dynamically adjusts the bit patterns stored in memory, ensuring that parity bits do not cycle excessively while maintaining their error correction function.

Inventive Principle:

Principle #15Dynamics

2Reliability

If message bits and parity bits are scrambled separately, then scrambling operation complexity increases, but synchronization of bit switching is improved

Engineering Contradiction:

Improvebit switching synchronizationVSAvoidscrambling operation complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines message bits and parity bits into a single codeword and applies one unified scrambling operation to the entire codeword. This approach maintains bit switching synchronization while avoiding the increased complexity that would result from performing separate scrambling operations on message bits and parity bits.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS10956259B2Error correction code memory device and codeword accessing method thereof

Publication Date: 2021.03.23 WINBOND ELECTRONICS CORP

AI summary

The codeword accessing method including: receiving a write data with M message bits; generating parity information with N-M bits based on an error correction algorithm and the M message bits, where N and M are positive integers; transforming the M message bits and the parity information to a scrambled codeword with N bits by a scrambling operation, where the scrambled codeword contains only a part of the M message bits; and writing the scrambled codeword into a memory device.