ECC Control Circuit for Multi-Channel Memory Systems
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Solution Overview
Problem
Data storage devices, particularly flash memories, face errors and malfunctions due to physical limitations, such as charge loss, temperature variations, and interference from adjacent cells, leading to inaccuracies in data reading and writing.
Innovation Solution
An Error Correcting Code (ECC) control circuit within a memory controller that includes ECC blocks and selectors to detect and correct errors in data read from multiple memory devices, ensuring accurate data transfer to a DMA buffer without reducing bus bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection and correction is performed on data from multiple memory devices, then data integrity is improved, but processing time and system complexity increase
Solution Approach 1:
The system divides error correction processing into separate ECC blocks for each memory device channel. Each ECC block independently handles error detection and correction for its corresponding memory device, allowing parallel processing and reducing the complexity burden on a single processing unit.
Solution Approach 2:
A multiplexer is introduced as an intermediary component that selectively routes data between the DMA buffer and ECC blocks. This intermediary manages the complex interactions between multiple memory channels, error correction units, and the DMA buffer, simplifying the overall system architecture by centralizing the routing logic.
2Reliability
If error correction is performed before DMA transfer, then data accuracy is improved, but transfer latency increases
Solution Approach 1:
The system dynamically adjusts the data routing based on error detection results. When errors are detected in data from a memory device, the multiplexer switches to route that channel's data through the corresponding ECC block for correction. When no errors are present, data is transferred directly through the DMA buffer, optimizing the balance between accuracy and latency on a per-channel basis.
Solution Approach 2:
Error correction is applied selectively to specific data channels that require it, rather than uniformly to all data. The ECC blocks and multiplexer enable local error correction only for affected memory channels, allowing error-free channels to maintain high-speed direct transfer while problematic channels receive correction processing.
3Quantity of substance
If multiple memory devices are used to increase storage capacity, then storage space is improved, but error frequency increases
Solution Approach 1:
The system segments storage across multiple memory device channels, each with its own dedicated ECC block for error correction. This segmentation allows the system to scale storage capacity by adding more channels while maintaining error correction capability for each individual channel, preventing error accumulation across the entire storage system.
Solution Approach 2:
Error detection and correction is performed preliminarily during the data read process before data is transferred to the host. The ECC blocks continuously monitor and correct errors in real-time as data is read from memory devices, preventing erroneous data from being transferred and ensuring high reliability even as storage capacity expands across multiple devices.
Data Source
AI summary
An Error Correcting Code (ECC) control circuit in a memory controller includes an ECC controller configured to receive data from a memory device in response to a request from a host device. The ECC controller transmits the data to a direct memory access (DMA) buffer for transfer to the host device, and to an ECC block for error detection and correction of the data. The ECC controller is configured to interrupt transmission of the data to the DMA buffer and transmit error-corrected data output from the ECC block to the DMA buffer responsive to detection of an error in the data by the ECC block. Related systems and methods are also discussed.