Memory ECC Using Cross-Over Bit Parity at Codeword Intersections
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Solution Overview
Problem
Memory devices face challenges in error correction, particularly when decoding data with block-wise concatenated codes, as they often reach an error floor where conventional methods fail to correct errors located at the intersections of column and row codewords, leading to decode failures.
Innovation Solution
Incorporating parity data for cross-over bits at the intersections of column and row codewords, which are used to correct errors through an XOR operation, enhancing the error correction capability of the ECC operation and potentially eliminating the need for an outer code.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC decoding methods are used for block-wise concatenated codes, then decoding operations can be performed with standard algorithms, but error correction fails when reaching the error floor at intersections of column and row codewords
Solution Approach 1:
The invention segments the error correction process into two distinct stages: first applying inner code decoding to correct errors in individual codewords, then applying outer code decoding to correct residual errors at intersections. This segmentation allows each decoder to specialize in specific error patterns, overcoming the error floor limitation of conventional single-stage decoding while maintaining manageable complexity through modular architecture.
Solution Approach 2:
The inner code decoding is performed as a preliminary action before outer code decoding. By first correcting errors within individual codewords using the inner code, the system prepares the data in a state where remaining errors are concentrated at intersections, making them more amenable to correction by the outer code in the subsequent stage.
2Reliability
If multiple outer code decoders are used to improve error correction at intersections, then correction capability increases, but device complexity and resource requirements increase
Solution Approach 1:
The invention merges the error correction functionality into a unified block-wise concatenated code structure where inner and outer codes work together in a coordinated manner. Instead of using multiple separate outer code decoders, the system combines the strengths of two different code types (inner and outer) in a single integrated decoding process, achieving superior intersection error correction with a single outer code decoder.
Solution Approach 2:
The block-wise concatenated code structure provides multi-functionality by handling both intra-codeword errors (through inner code) and inter-codeword intersection errors (through outer code) within a single ECC operation framework. This universal approach eliminates the need for multiple specialized decoders while maintaining comprehensive error correction capability.
3Reliability
If outer code is used to correct intersection errors, then error correction improves, but the system requires additional outer code decoder resources
Solution Approach 1:
The outer code is specifically designed to target and correct errors at the local intersection regions where column and row codewords meet. By concentrating the outer code's correction capability on these specific problematic locations rather than distributing resources across all data bits, the system achieves effective intersection error correction with minimal decoder resources.
Solution Approach 2:
The outer code decoding performs partial action by focusing only on correcting residual errors at intersections after inner code decoding, rather than attempting to correct all errors from scratch. This partial approach reduces the computational burden and resource requirements compared to using a single comprehensive decoder, while still achieving sufficient overall correction capability.
Data Source
AI summary
Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include encoding data by including parity data for a number of cross-over bits, wherein the number of cross-over bits are bits located at intersections of column codewords and row codewords.