ECC Circuit Data Splitting and Scrambling for DRAM Error Correction
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Solution Overview
Problem
Dynamic Random Access Memory (DRAM) devices face challenges in correcting specific patterns of errors that cannot be addressed by existing error correction code (ECC) circuits, leading to unrecoverable data errors due to structural defects in the memory cell array.
Innovation Solution
The implementation of an ECC circuit that splits input data into sub-data, performs ECC encoding on each sub-data to generate sub-parity data, and applies a data scrambling operation based on the memory cell array structure to generate write data, ensuring that each memory cell stores 2-bit symbols corresponding to the ECC codes, thereby correcting specific patterns of errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ECC encoding is applied to all data uniformly, then the error correction capability is limited to standard patterns, but specific pattern errors occurring in DRAM cannot be corrected
Solution Approach 1:
The input data is divided into multiple sub-data groups (e.g., first sub-data and second sub-data), and separate ECC encoding is performed on each sub-data group to generate corresponding sub-parity data. This segmentation allows the system to handle different error patterns in different data segments independently, improving the ability to correct specific pattern errors while maintaining overall reliability.
2Ease of manufacture
If data is stored directly without scrambling, then the storage process is simple, but errors specific to certain memory cell patterns cannot be corrected
Solution Approach 1:
A data scrambling operation is performed on the sub-data and sub-parity data before storage, based on the structure of the memory cell array. This preliminary scrambling redistributes the data bits across different physical memory locations, ensuring that specific pattern errors (such as those affecting adjacent cells or cells connected to the same sense amplifier) are transformed into random-like error patterns that can be corrected by the ECC decoding process.
3Quantity of substance
If multiple 2-bit symbols per sub-data are stored in memory cells, then more data can be stored, but error correction for specific patterns becomes non-uniform and complex
Solution Approach 1:
The patent ensures that only one 2-bit symbol per sub-data is stored in memory cells corresponding to one local sense amplifier. This local quality constraint creates a uniform distribution pattern where each sense amplifier handles a specific, limited subset of data symbols. This uniformity simplifies the error correction process because the ECC decoder can systematically process errors based on the known mapping between sense amplifiers and data symbols, reducing complexity despite maintaining storage capacity.
Data Source
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AI summary
A memory device includes an ECC circuit that performs error correction code (ECC) encoding on input data to generate write data, and a memory cell array including a plurality of memory cells that stores the write data. The ECC circuit includes a data splitter that splits the input data into first sub-data and second sub-data, a first ECC encoder that performs ECC encoding on the first sub-data to generate first sub-parity data, a second ECC encoder that performs ECC encoding on the second sub-data to generate second sub-parity data, and a data scrambler that performs a data scrambling operation with respect to the first sub-data, the second sub-data, the first sub-parity data, and the second sub-parity data based on a structure of the memory cell array to generate the write data.