Memory Channel ECC-DBI-DM Pipeline for Lower Write Latency
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Solution Overview
Problem
Current memory systems face challenges in optimizing area, power consumption, and operating time due to the limitations of existing ECC, DBI, and DM unit operations, particularly in parallel operation and error handling, which leads to increased latency and power consumption.
Innovation Solution
A memory system that includes an ECC unit for error correction, a DBI unit for data inversion, and a DM unit that operates independently to minimize high logic bits, reducing power consumption and optimizing operations by generating flags based on data patterns and error corrections, allowing the DM unit to function regardless of single error occurrences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the DM unit operates dependently on the ECC unit, then error correction can be performed, but the operating time and latency increase
Solution Approach 1:
The patent segments the error handling functionality into two independent units: the ECC unit for error correction and the DM unit for data masking flag generation. By dividing these functions, the DM unit can operate independently to generate masking flags without waiting for the ECC unit to complete error correction, thereby reducing operating time and latency while maintaining reliability.
2Loss of information
If all data bits are transmitted through the channel, then complete data can be received, but power consumption increases due to high logic bits
Solution Approach 1:
The patent extracts and transmits only the essential data bits that need to be communicated, using the DM unit to generate masking flags that indicate which data bits should be masked or ignored. This extraction approach reduces the number of high logic bits transmitted through the channel, thereby reducing power consumption while maintaining data completeness through the use of masking flags.
Solution Approach 2:
The patent changes the parameter of data transmission by introducing masking flags that modify how data bits are interpreted. Instead of transmitting all data bits with equal weight, the masking flags allow the receiver to selectively process or ignore certain bits, effectively changing the transmission parameter to reduce power consumption associated with high logic bits.
3Reliability
If the DM unit processes data after ECC correction, then accurate error-corrected data is available, but the area and operating time increase
Solution Approach 1:
The patent segments the data processing pipeline into parallel independent units: the ECC unit for error correction and the DM unit for masking flag generation. This segmentation allows both units to operate simultaneously on different aspects of data handling, eliminating the need for sequential processing and reducing the overall area and time requirements while maintaining data accuracy.
4Productivity
If the DM unit operates in parallel with ECC and DBI units, then operating time is reduced, but device complexity increases
Solution Approach 1:
The patent segments the memory system into distinct functional units (ECC unit, DBI unit, and DM unit) that can operate in parallel. Each unit has a specific, well-defined function, which simplifies the control logic for each individual unit while enabling overall parallel operation that improves productivity without excessive complexity.
Data Source
AI summary
A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.