ECC Decode Scheduling for Autonomous Multi-Phase Error Correction

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Solution Overview

Problem

The complexity of designing and implementing multi-phase error correction coding (ECC) decoders in non-volatile data storage devices increases due to the need for multiple decoding phases and the generation of redundant information, making it challenging to correct errors effectively.

Innovation Solution

A schedule-based ECC decode controller populates a decoding schedule for data chunks, initiating decoding in a pipelined operation with stages for fetching, decoding, and writing back, using a stack or stack-on-stack configuration to manage data chunks and parity bits, allowing for reduced complexity and self-sustained operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multi-phase ECC decoding is implemented to increase error correction capacity, then error correction capability is improved, but device complexity increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoiddecoder complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The ECC decoding process is segmented into multiple phases: a first phase using a reduced set of parity bits for initial decoding attempts, and a second phase using a larger set of parity bits for more powerful decoding when the first phase fails. This segmentation allows the system to achieve high error correction capability while managing complexity by breaking down the decoding task into manageable stages.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary decoding using a reduced set of parity bits before attempting full decoding with the complete parity bit set. This preliminary action filters out many decoding cases that can be resolved with minimal resources, reserving the more complex full decoding process only for cases that truly require it, thereby reducing overall operational complexity.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If a larger set of parity bits is used for powerful decoding, then error correction capacity increases, but the number of bits required to store encoded data increases

Engineering Contradiction:
Improveerror correction capacityVSAvoidnumber of bits
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The parity bits are segmented into a reduced set and a larger set. The reduced set is used for initial decoding attempts on individual chunks, while the larger set is reserved for secondary decoding when needed. This segmentation allows the system to maintain high error correction capacity while reducing the average number of bits stored and processed for each chunk.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system applies partial decoding using only the reduced set of parity bits for most chunks, and applies the full larger set of parity bits only when necessary (excessive action). This approach ensures that the majority of decoding operations use fewer bits, while maintaining the capability to handle difficult error cases with the complete parity bit set.

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If multi-phase ECC decoding is implemented, then error correction capability is improved, but implementation complexity and debugging difficulty increase

Engineering Contradiction:
Improveerror correction capabilityVSAvoidimplementation ease
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The ECC decode controller autonomously manages the multi-phase decoding process by automatically determining when to transition from the first phase to the second phase based on decoding success or failure. This self-service approach eliminates the need for complex external control logic and simplifies implementation, as the controller independently handles the complexity of phase management and debugging.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system uses feedback from the first phase decoding results to control the transition to the second phase. When decoding fails in the first phase, the system automatically triggers the second phase with the larger parity bit set. This feedback mechanism simplifies implementation by providing clear, automated decision-making logic rather than requiring complex external control.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8954816B2Error correction coding (ECC) decode operation scheduling
Publication Date: 2015.02.10 SANDISK TECHNOLOGIES LLC
  • US8954816B2 patent drawing
  • US8954816B2 patent drawing
  • US8954816B2 patent drawing

AI summary

A method includes receiving, at an error correction coding (ECC) controller, information indicating one or more data chunks to be decoded, populating a schedule according to an order of decoding of the data chunks, and initiating decode of the data chunks according to the schedule.