ECC Decoder Logic for Block-Localized Memory Error Correction
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Solution Overview
Problem
Memory chips with decreasing feature sizes exhibit higher bit error rates, leading to faulty error correction that can introduce additional errors, causing the memory controller's ECC algorithm to fail in correcting cache lines due to scattered error positions within the code word.
Innovation Solution
The ECC algorithm is improved by constraining additional errors to be introduced near the original incorrect bits within the raw data portion or within the check bits of the code word, using a structured approach with Cayley tables to guide the selection of valid code words and parity check matrices, ensuring that errors are contained within specific blocks or the check bits portion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory chip feature sizes are decreased to increase storage capacity, then storage density is improved, but bit error rate increases leading to faulty error correction
Solution Approach 1:
The code word is divided into multiple blocks, and errors are constrained to be corrected within the same block where they originated. This segmentation prevents scattered error positions from exceeding the controller's correction threshold and maintains reliability while allowing smaller feature sizes for higher storage density.
2Reliability
If traditional ECC correction is applied to scattered errors, then error correction is attempted, but additional errors are introduced causing correction failure
Solution Approach 1:
The error correction process applies different treatment to different blocks of the code word. Errors are identified and constrained to be corrected within their original block, creating a localized correction approach that prevents the introduction of additional scattered errors that would harm reliability.
3Measurement precision
If errors are scattered throughout the code word, then comprehensive error detection is achieved, but correction threshold is exceeded causing failure
Solution Approach 1:
The code word is segmented into blocks, and the correction process ensures that errors remain confined to their original blocks. This maintains comprehensive error detection capability while preventing the scattering of corrected errors that would exceed the controller's correction threshold and cause reliability failures.
Data Source
AI summary
An apparatus is described. The apparatus includes a memory chip. The memory chip has an error correction code (ECC) encoder logic circuit and an ECC decoder logic circuit. The ECC decoder logic circuit is to place an additional one or more errors that result from incorrect error correction applied to a read code word into a same block of multiple blocks of the read code word's raw data bit portion where original errors in the read code word existed before the read code word was decoded by the ECC decoder logic circuit.