ECC Decoder Buffering for Low-Latency Defective Sector Re-Read

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Solution Overview

Problem

As semiconductor memory devices, such as flash memory, are scaled down and memory cells are stacked, they experience degradation, leading to reduced data retention and increased latency in error correction coding (ECC) decoding processes.

Innovation Solution

An ECC decoder is introduced, comprising an input manager, a pre-decoder, and a main decoder. The input manager receives data from a nonvolatile memory device, the pre-decoder generates syndromes for each data unit, and the main decoder performs ECC decoding. A defective sector buffer is used to store data units with failed ECC decoding, allowing for selective storage based on expected error counts, and subsequent re-decoding with offset read voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory cells are stacked and fabrication process is scaled-down to increase storage capacity, then storage density is improved, but data retention characteristic is degraded

Engineering Contradiction:
Improvestorage capacityVSAvoiddata retention characteristic
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent segments the ECC decoding process into multiple stages: first ECC decoding on original read data, followed by second ECC decoding on re-read data for defective data units. This segmentation allows the system to handle degraded data retention characteristics by processing different portions of data through different decoding paths, thereby maintaining overall system reliability despite memory cell degradation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary identification of defective data units through first ECC decoding before attempting second ECC decoding. By预先 (in advance) identifying which data units require re-reading and soft-decision decoding, the system prepares for potential retrieval failures caused by scaled-down memory degradation, thus preventing complete decoding failure.

Inventive Principle:
Principle #10Preliminary action

2Device complexity

If conventional ECC decoding is performed on degraded memory data, then decoding process is simple, but latency increases due to repeated failed decoding attempts

Engineering Contradiction:
Improvedecoding process complexityVSAvoiddecoding latency
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent performs preliminary hard-decision ECC decoding on all read data to identify defective data units before initiating soft-decision decoding. This preliminary action filters out data units that need special handling, allowing the system to avoid unnecessary soft-decision decoding on good data units and thus reducing overall latency despite the added complexity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces a defective sector buffer as an intermediary component that stores identified defective data units for subsequent soft-decision decoding. This intermediary structure separates the fast path (for good data) from the slow path (for defective data), enabling parallel processing and reducing the impact of complex decoding on overall latency.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If soft-decision decoding is performed on all data units, then error correction success rate is improved, but latency increases due to processing overhead

Engineering Contradiction:
Improveerror correction success rateVSAvoidsoft-decision decoding latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies soft-decision decoding only partially - specifically to defective data units identified by hard-decision decoding - rather than to all data units. This partial application of the more reliable but slower soft-decision decoding method achieves improved error correction success rate for problematic data while avoiding the excessive latency that would result from applying it universally.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent applies different decoding qualities to different data units: hard-decision decoding for most data units and soft-decision decoding only for defective data units. This local differentiation of decoding quality ensures that the higher reliability of soft-decision decoding is applied only where needed, optimizing the balance between error correction success rate and latency.

Inventive Principle:
Principle #3Local quality

4Measurement precision

If defective data units are stored in buffer for re-decoding, then error correction accuracy is improved, but device complexity increases

Engineering Contradiction:
Improveerror detection accuracyVSAvoidbuffer management complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent introduces a defective sector buffer as an intermediary storage component that temporarily holds defective data units for re-decoding. This intermediary buffer simplifies the overall system architecture by providing a dedicated storage location for problematic data, making the error correction process more manageable despite the added component.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent extracts defective data units from the main data stream and places them in a separate buffer for specialized processing. This extraction isolates the complex error correction task to only the necessary data units, reducing the overall complexity of buffer management compared to handling all data units uniformly.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS12273127B2Error correction code decoder, storage controller and storage device
Publication Date: 2025.04.08 SAMSUNG ELECTRONICS CO LTD
  • US12273127B2 patent drawing
  • US12273127B2 patent drawing
  • US12273127B2 patent drawing

AI summary

An Error correction code (ECC) decoder including an input manager configured to sequentially receive a first read data including a plurality of data units read from a plurality of sectors in a memory cell array of a nonvolatile memory device, by unit of sector, a pre-decoder configured to sequentially receive the first read data and generate a respective syndrome of each of the data units, and a main decoder configured to sequentially perform a first ECC decoding on the first read data based on the respective syndrome. The input manager includes a defective sector buffer to store a data unit having a minimum expected error count from among data units on which a first ECC decoding is failed. The main decoder performs a second ECC decoding on a defective data unit stored in the defective sector buffer and receives a second read data from a selected sector corresponding to the defective data unit.