ECC Decoder Logic for Low-Latency Single and Multiple Error Correction

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Solution Overview

Problem

As data transmission speeds increase and storage densities rise, higher bit error rates (BERs) become more likely, requiring larger codewords with more parity bits, which in turn demand complex algorithms and increased computing resources, potentially leading to unacceptable latency in memory access times for non-volatile memory technologies like 2LM and SSDs.

Innovation Solution

Implementing techniques that allow for efficient error correction in ECC encoded data by identifying single errors quickly to reduce latency, using algorithms such as Berlekamp-Massey and Chien Search, and employing ECC decoder logic to generate flags for multiple errors, enabling separate identification and correction of error locations and values, thereby reducing the computational intensity required for error correction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If larger codewords with more parity bits are used to reduce BER, then error correction capability is improved, but computing resource usage and algorithm complexity increase

Engineering Contradiction:
Improveerror correction capabilityVSAvoidalgorithm complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The error correction process is segmented into two distinct phases: a fast single-error correction path and a comprehensive multiple-error correction path. The syndrome calculator determines which path to take, allowing the system to handle errors efficiently without always invoking the full complex algorithm suite.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs partial error correction by first attempting quick single-error correction using simplified logic. Only when this partial approach fails does it proceed to the full multiple-error correction algorithm, avoiding unnecessary computational overhead while maintaining complete error correction capability.

Inventive Principle:
Principle #16Partial or excessive action

2Reliability

If larger codewords with more parity bits are used to reduce BER, then error correction capability is improved, but memory access latency increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidmemory access latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The correction process is divided into a fast path for single errors and a slower path for multiple errors. By segmenting the workflow, the system can quickly resolve the common single-error case without incurring the full latency penalty of complex algorithms, thereby reducing average access time.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system applies partial correction for single errors using streamlined logic, which is sufficient for the majority of error cases. This partial approach significantly reduces processing time compared to always applying full error correction, while maintaining reliability for more severe error conditions.

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If complex algorithms are used to correct multiple errors, then error correction capability is improved, but computing resource usage increases

Engineering Contradiction:
Improvemultiple error correction capabilityVSAvoidcomputing resource usage
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The algorithm suite is segmented into a lightweight single-error handler and a resource-intensive multiple-error handler. The syndrome calculator acts as a gatekeeper, directing simple cases to the lightweight path and reserving complex algorithm execution only for necessary multiple-error scenarios, optimizing resource utilization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system applies minimal necessary correction for single errors, avoiding the excessive computational resources required for full multiple-error correction. This partial application of correction logic significantly reduces energy consumption while maintaining adequate protection for typical error conditions.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS8990655B2Techniques associated with error correction for encoded data
Publication Date: 2015.03.24 SK HYNIX NAND PRODUCT SOLUTIONS CORP
  • US8990655B2 patent drawing
  • US8990655B2 patent drawing
  • US8990655B2 patent drawing

AI summary

Examples are disclosed for techniques associated with error correction for encoded data. In some examples, error correction code (ECC) information for the ECC encoded data is received that indicates the ECC encoded data includes one or more errors. A determination is made as to whether the ECC encoded data includes either a single error or more than one error. If the ECC encoded data includes a single error, an error location of the error is identified. If the ECC encoded data includes more than one error, separate error locations are identified for the more than one error. The single error or the more than one error is corrected and the ECC encoded data is then be decoded.