ECC Decoder Latency Reduction in Semiconductor Memory Devices
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing bit errors in DRAMs due to shrinking fabrication design rules lead to decreased yield and reliability of semiconductor memory devices, necessitating effective error correction mechanisms.
Innovation Solution
A semiconductor memory device incorporating a memory cell array, an error correction circuit with an ECC decoder, and a control logic circuit that performs t-bit error correction, generating a syndrome, error locator polynomial, and correcting errors based on the polynomial to reduce latency and improve data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fabrication design rules are shrunk to increase memory density, then memory capacity is improved, but bit error rate increases
Solution Approach 1:
The patent applies preliminary action by performing error correction decoding before data is fully processed or used. The ECC decoder corrects bit errors in read data before the data is output to the memory controller, preventing error propagation and ensuring data integrity is maintained even as memory density increases through fabrication shrinkage.
2Reliability
If error correction capability is enhanced to correct more bit errors, then reliability is improved, but decoding latency increases
Solution Approach 1:
The patent segments the error correction process into distinct functional modules: syndrome generation unit, error location identification unit, and error correction unit. This segmentation allows each module to perform its specific function efficiently and in parallel where possible, reducing overall decoding latency while maintaining strong error correction capability.
Solution Approach 2:
The patent replaces traditional iterative error correction algorithms with a direct algebraic approach using Berlekamp-Massey algorithm for syndrome calculation and error location identification. This substitution eliminates iterative loops and complex control logic, achieving faster error correction with reduced latency while maintaining the ability to correct multiple bit errors.
3Reliability
If complex error correction algorithms are used to correct multiple bit errors, then error correction capability is improved, but circuit complexity increases
Solution Approach 1:
The patent replaces complex iterative error correction algorithms with direct algebraic computations using Berlekamp-Massey syndrome calculation and polynomial-based error location identification. This substitution transforms a control-intensive iterative process into a series of straightforward arithmetic operations, reducing circuit complexity while maintaining the ability to correct t-bit errors.
Solution Approach 2:
The patent changes the operational parameters of the error correction circuit by using pre-defined generator polynomials and systematic syndrome calculation methods. This approach transforms the error correction process from one requiring dynamic algorithm selection and iterative adjustment to a fixed-parameter computation system, simplifying the circuit design while preserving strong error correction capability.
Data Source
AI summary
A semiconductor memory device includes a memory cell array, an error correction circuit and a control logic circuit. The error correction circuit includes an error correction code (ECC) decoder to perform an ECC decoding on a codeword including a main data and a parity data, read from a target page of the memory cell array to correct errors in the read codeword. The control logic circuit controls the error correction circuit based on a command and address from an external memory controller. The ECC decoder has t-bit error correction capability, generates a syndrome based on the codeword using a parity check matrix, performs t iterations during (t−2) cycles to generate an error locator polynomial based on the syndrome, searches error positions in the codeword based on the error locator polynomial and corrects the errors in the codeword based on the searched error positions.