ECC Decoder Using Partial Sub-Matrices for Low-Parity Memory Correction

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Solution Overview

Problem

Existing memory devices face challenges in efficiently correcting and managing errors that occur in memory modules, particularly when the number of parity data sets is less than the number of bits in the main data and metadata sets.

Innovation Solution

An error correction circuit and method that utilize a few parity bits to correct errors in a plurality of memory devices. The circuit includes an ECC encoder to generate parity data based on a parity generation matrix and an ECC decoder to read codewords from memory devices, generate syndromes, detect error patterns, and correct errors by comparing syndromes with estimation syndromes generated using partial sub-matrices of a parity check matrix.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a traditional ECC method using sufficient parity bits is used, then error correction capability is improved, but memory resource consumption increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidmemory resource consumption
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The parity check matrix is divided into multiple sub-matrices, each corresponding to a specific error pattern type. During decoding, only the relevant sub-matrix is selected and applied based on the syndrome pattern, rather than using the complete parity check matrix. This segmentation allows efficient error correction while reducing the computational and storage resources needed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically changes the parameter of the parity check matrix by selecting different sub-matrices based on the error pattern detected in the syndrome. This parameter change enables the system to adapt to different error scenarios using minimal parity bits, achieving high error correction capability without requiring excessive memory resources for storing multiple complete parity check matrices.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If more parity data sets are provided, then error correction accuracy is improved, but the overhead and complexity of the memory system increases

Engineering Contradiction:
Improveerror correction accuracyVSAvoidsystem overhead
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

Instead of providing complete parity check coverage for all possible error patterns, the system uses partial action by selecting and applying only the specific sub-matrix relevant to the detected error pattern. This approach achieves accurate error correction for the actual error scenarios encountered without the overhead of implementing complete parity check matrices for all possible errors.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The system changes the parameter of the parity check operation by dynamically selecting different sub-matrices based on the syndrome analysis. This parameter change allows the system to maintain high error correction accuracy for relevant error patterns while avoiding the complexity of implementing and storing multiple complete parity check matrices.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If a comprehensive parity check matrix is used for all error patterns, then error detection coverage is improved, but the time and computational resources required for error correction increase

Engineering Contradiction:
Improveerror detection coverageVSAvoiderror correction time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The parity check matrix is segmented into multiple sub-matrices, each handling specific error patterns. During error correction, the system first analyzes the syndrome to identify the error pattern type, then selects only the corresponding sub-matrix for correction. This segmentation dramatically reduces the computational time and resources required compared to applying a comprehensive parity check matrix to all error patterns.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary analysis of the syndrome to identify the error pattern type before applying the parity check correction. This preliminary action enables the system to pre-select the appropriate sub-matrix, avoiding the time-consuming process of applying a comprehensive parity check matrix and then filtering results. The preliminary classification step significantly reduces overall error correction time.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12212339B2Error correction circuit, memory system, and error correction method
Publication Date: 2025.01.28 SAMSUNG ELECTRONICS CO LTD
  • US12212339B2 patent drawing
  • US12212339B2 patent drawing
  • US12212339B2 patent drawing

AI summary

An error correction circuit, including an error correction code (ECC) encoder configured to generate parity data corresponding to main data based on a parity generation matrix, and to output a codeword including the main data and the parity data to a plurality of memory devices; and an ECC decoder configured to: read the codeword from the plurality of memory devices, generate a syndrome corresponding to the codeword based on a parity check matrix, detect an error pattern based on the syndrome, generate a plurality of estimation syndromes corresponding to the error pattern using a plurality of partial sub-matrices included in the parity check matrix, and correct an error included in the read codeword based on a result of a comparison between the syndrome and the plurality of estimation syndromes.