ECC Decoder Using Syndrome and Message Checks for Memory Bit Errors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memory devices face increased bit errors and decreased yield due to shrinking fabrication design rules, necessitating enhanced error correction capabilities without increasing parity overhead.
Innovation Solution
An error correction code (ECC) decoder and semiconductor memory device design that generates characteristic information and syndrome vectors to detect and correct errors in codewords, using a parity check matrix to selectively correct error bits and generate flag signals, thereby enhancing error detection and correction capabilities without increasing parity overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fabrication design rules are shrunk to increase memory capacity, then storage density is improved, but bit error rate increases and yield decreases
Solution Approach 1:
The codeword is divided into message bits and parity bits, with the parity bits used for error detection and correction. The ECC decoder separately processes these segments to identify and correct errors without affecting the entire data set.
Solution Approach 2:
The patent changes the parameter of error detection capability by generating characteristic information from message bits and combining it with syndrome vectors, enabling enhanced error detection without changing the physical fabrication parameters.
2Reliability
If traditional ECC methods are used for error correction, then error correction capability is maintained, but error detection capability is insufficient
Solution Approach 1:
The ECC decoder generates characteristic information from message bits and uses it as feedback in the error detection process. This feedback mechanism enables the system to distinguish between errors in message bits and parity bits, enhancing overall error detection capability.
Solution Approach 2:
The patent combines characteristic information (generated from message bits) with syndrome vectors (generated from parity check matrix operations) to create a composite error detection mechanism that is more powerful than traditional single-method ECC approaches.
3Measurement precision
If more parity bits are added to improve error detection, then error detection capability is improved, but parity overhead increases
Solution Approach 1:
The characteristic information generated from message bits serves multiple functions: it enhances error detection capability, helps distinguish error locations, and works in conjunction with traditional syndrome vectors. This multi-functionality allows improved error detection without adding dedicated parity bits.
Solution Approach 2:
Instead of increasing the number of parity bits, the patent changes the processing parameter by generating and utilizing characteristic information from existing message bits, achieving enhanced error detection capability without increasing parity overhead.
Data Source
AI summary
An error correction code (ECC) decoder of a semiconductor memory device is provided. The ECC decoder includes an ECC checker, a syndrome generator, and an error detection/correction circuit. The ECC checker generates characteristic information representing first error information associated with message bits in an input codeword that is read from a target page in a memory cell array. The syndrome generator outputs a syndrome vector representing second error information associated with the input codeword by performing an operation on the message bits and parity bits in the input codeword based on a parity check matrix. The an error detection/correction circuit generates a transmission codeword by selectively correcting an error bit in the input codeword based on the characteristic information and the syndrome vector, generates a flag signal indicating whether the transmission codeword includes an error bit, and outputs a transmission message based on the transmission codeword.