ECC Decoder Reliability Mapping for Multi-Level Cell Memory
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Solution Overview
Problem
Nonvolatile memory devices with multi-level cells face challenges in error correction due to increased degeneration and decreased operation speeds, particularly in maintaining high error correction probabilities without additional read operations.
Innovation Solution
An ECC decoder is implemented with a buffer, data converter, and decoding circuit that adjusts reliability parameters based on state-bit mapping information, performing initial and re-decoding operations to enhance error correction probabilities in multi-level cell memory systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cell scheme is used to increase memory capacity, then memory capacity increases, but error correction probability decreases and operation speed decreases
Solution Approach 1:
The memory cells connected to the same wordline are divided into multiple read pages (first read page, second read page, third read page), each containing different bits. This segmentation allows the ECC decoder to process and correct errors in each page separately, improving overall error correction probability while maintaining high memory capacity through the multi-level cell scheme.
Solution Approach 2:
The buffer stores multiple read pages before ECC decoding is performed. This preliminary storage allows the decoding circuit to access all necessary data pages in advance, enabling comprehensive error correction across multiple pages without requiring additional read operations during the correction process.
2Quantity of substance
If multi-level cell scheme is used to increase memory capacity, then memory capacity increases, but operation speed decreases
Solution Approach 1:
By segmenting the error correction process into separate decoding operations for each read page stored in the buffer, the system can process multiple pages in parallel or sequentially without requiring additional read operations, thereby maintaining operation speed while handling increased memory capacity.
Solution Approach 2:
Multiple read pages are preliminarily stored in the buffer before decoding, allowing the decoding circuit to perform comprehensive error correction without needing to perform additional read operations during the correction process, thus maintaining operation speed.
3Reliability
If additional read operations are performed to improve error correction probability, then error correction probability increases, but operation speed decreases
Solution Approach 1:
The buffer stores multiple read pages in advance before ECC decoding is performed. This preliminary storage eliminates the need for additional read operations during the error correction process, allowing the decoding circuit to access all necessary data pages immediately and maintain high operation speed while achieving high error correction probability.
Data Source
AI summary
An error check code (ECC) decoder includes a buffer, a data converter and a decoding circuit. The buffer stores a plurality of read pages read from a plurality of multi-level cells connected to a same wordline. The data converter adjusts reliability parameters of read bits of the plurality of read pages based on state-bit mapping information and the plurality of read pages to generate a plurality of ECC input data respectively corresponding to the plurality of read pages. The state-bit mapping information indicate mapping relationships between states and bits stored in the plurality of multi-level cells. The decoding circuit performs an ECC decoding operation with respect to the plurality of read pages based on the plurality of ECC input data. An error correction probability is increased by adjusting the reliability parameters of read bits based on the state-bit mapping information.