ECC Decoder Reset Attack Detection in Memory Arrays
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, the resistance of conductive lines within these digital devices changes, affecting operating voltages and overall IC performance. Additionally, there is a need to detect reset attacks on memory cell arrays without using separate sensors, which would occupy more area.
Innovation Solution
The integrated circuit includes an ECC encoder, a first memory cell array, and an ECC decoder. The ECC encoder generates a first set of check bits in response to data, which are stored in an inverted form in the first memory cell array. Before decoding, the check bits are inverted again to generate a second set of check bits, which are then decoded to detect or correct errors. This configuration allows for the detection of reset attacks without a separate sensor, optimizing area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate sensors are used to detect reset attacks on memory cell arrays, then detection capability is improved, but the area occupied by the integrated circuit increases
Solution Approach 1:
The patent merges the reset attack detection function with the existing ECC decoder by adding an attack detection logic unit that shares the same hardware resources. The ECC decoder normally decodes check bits to detect storage errors, but the enhanced version also detects reset attacks by analyzing whether all check bits are simultaneously valid, indicating a potential reset attack rather than random bit flips.
Solution Approach 2:
The ECC decoder is designed to perform multiple functions: traditional error detection and correction, and reset attack detection. By making the decoder multi-functional, the patent eliminates the need for separate dedicated sensors, thereby maintaining detection capability while reducing the overall circuit area.
2Area of stationary object
If IC size is reduced to improve portability and integration, then area is reduced, but resistance of conductive lines changes affecting operating voltages and performance
Solution Approach 1:
The patent implements different voltage threshold levels for different types of errors in the attack detection logic. By setting specific voltage thresholds that distinguish between normal storage errors (caused by line resistance changes) and reset attacks, the system can reliably detect attacks even in miniaturized circuits where resistance characteristics have changed.
Data Source
AI summary
An integrated circuit includes a first memory cell array configured to store a first set of data, a second memory cell array configured to store a first inverted set of check bits, a first set of inverters and an error correction code (ECC) decoder. The first set of inverters is configured to generate a second set of check bits in response to a third set of check bits inverted from the second set of check bits. The third set of check bits corresponds to the first inverted set of check bits stored in the second memory cell array. The ECC decoder is configured to detect or correct an error in a second set of data or the second set of check bits thereby generating a set of output data and a been-attacked signal. The been-attacked signal indicating a reset attack by a user.