ECC Decoder Circuit Using Shared Arithmetic to Cut DRAM Area
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in reducing the area occupied by error correction code (ECC) circuits while maintaining effective error correction capabilities, particularly in DRAM devices with increasing memory capacity.
Innovation Solution
Implementing an ECC circuit with reduced circuit complexity by utilizing a common arithmetic circuit for syndrome decoding and eliminating unnecessary arithmetic circuits, based on the structure of the parity-check matrix (H-matrix), which includes an ECC encoder and decoder configured to perform operations without redundant logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ECC circuits are implemented in DRAM devices with increasing memory capacity, then error correction capability is maintained, but the area occupied by the ECC circuit increases
Solution Approach 1:
The patent combines multiple arithmetic operations (syndrome calculation, error pattern identification, and error correction) into a single integrated ECC circuit structure. The syndrome generator, error pattern generator, and error correction unit share common arithmetic resources and data pathways, merging previously separate functional blocks into a unified circuit that reduces overall area while maintaining full error correction capability.
Solution Approach 2:
The ECC circuit is designed with universal arithmetic units that can perform multiple functions. The same arithmetic logic is used for both syndrome calculation during encoding and for error pattern identification during decoding. This multi-functional design eliminates the need for dedicated arithmetic circuits for each function, significantly reducing the total circuit area while preserving comprehensive error correction capabilities.
2Measurement precision
If comprehensive ECC decoding operations are implemented, then error correction accuracy is improved, but device complexity increases
Solution Approach 1:
The ECC decoding process is segmented into distinct functional stages: syndrome generation, error pattern identification, and error correction application. Each stage is implemented as a separate modular unit with dedicated input and output interfaces. This segmentation allows for optimized design of each individual stage while maintaining the overall accuracy of the complete decoding process, and facilitates easier verification and testing.
Solution Approach 2:
The circuit performs preliminary syndrome calculation and error pattern identification before the actual error correction is applied to the data. By pre-computing the syndrome and determining the error pattern in advance, the circuit prepares all necessary correction information beforehand, which simplifies the final correction step and reduces the complexity of real-time decision-making during the correction process.
Data Source
AI summary
Disclosed is a memory device which includes an input/output circuit receiving first data and first parity data from a memory controller, an ECC encoder generating parity check data based on the first data, a syndrome generator generating a syndrome based on the parity check data and the first parity data, an error vector generator performing ECC decoding based on the syndrome and generating an error vector, an error correction circuit generating error-corrected data based on the error vector, the first data, and the first parity data, and a memory cell array storing the error-corrected data. The error vector generator includes an arithmetic circuit performing a common operation associated with the ECC decoding based on the syndrome and generating a common arithmetic signal, and a plurality of comparison circuits generating the error vector based on the syndrome and the common arithmetic signal.