ECC Decoder Parameter Adjustment for Inaccurate Soft Bits
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Solution Overview
Problem
Error correction code (ECC) decoders in non-volatile data storage devices face performance degradation due to inaccuracies in soft bits, particularly when single-level cell data is 'folded' into tri-level cells or when errors occur in long error tails, leading to incorrect reliability assessments and reduced correction capabilities.
Innovation Solution
The system dynamically adjusts decode parameters based on actual error counts and bit counts associated with decoded portions of data, using log likelihood ratio (LLR) values and other parameters to improve the accuracy of error correction, by calculating adjusted LLR values and providing them as input to the ECC decoder.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If soft bits are used to indicate reliability of hard bits, then error correction capability is improved, but accuracy of reliability information deteriorates when errors are not concentrated in state overlap regions
Solution Approach 1:
The patent applies dynamics by making the decoding process adaptive through multiple decoding attempts with varying parameters. The system dynamically adjusts decoding thresholds and parameters based on whether errors are concentrated in state overlap regions or distributed differently, allowing the decoder to optimize its behavior for the actual error pattern encountered rather than relying on static soft bit reliability indicators.
Solution Approach 2:
The patent changes decoding parameters dynamically during the error correction process. Different decoding thresholds, iteration counts, and algorithm parameters are applied based on the detected error pattern. This allows the system to adapt to different error distributions (concentrated in overlap regions vs. distributed elsewhere) and maintain high correction capability even when soft bit reliability information is inaccurate.
2Quantity of substance
If blind On-Chip-Copy operation is used to fold SLC data into TLCs, then storage capacity is increased, but accuracy of soft bits deteriorates leading to incorrect reliability assessments
Solution Approach 1:
The patent introduces an intermediary error detection and analysis mechanism between the storage medium and the final decoding process. This intermediary layer analyzes the actual error patterns in the folded data and uses this information to adjust decoding parameters, effectively mediating between the inaccurate soft bit reliability information and the decoding process to achieve correct error correction.
Solution Approach 2:
The patent implements feedback by using the results of initial decoding attempts and error detection to adjust subsequent decoding parameters. The system monitors decoding performance and feeds this information back to modify the decoding process, allowing it to compensate for inaccurate soft bit reliability information generated during the folding operation.
3Device complexity
If static decode parameters are used, then device complexity is reduced, but error correction performance deteriorates when error patterns vary
Solution Approach 1:
The patent applies dynamics by implementing multiple decoding modes with different parameters that can be selected based on the detected error pattern. Rather than using a single static set of parameters, the system dynamically switches between different decoding configurations (e.g., different thresholds, iteration counts, or algorithm variants) to match the actual error characteristics, thereby maintaining high correction performance without excessive complexity.
Solution Approach 2:
The patent segments the decoding process into multiple stages or modes, each optimized for different error patterns. By dividing the overall error correction task into separate decoding attempts with different parameter sets, the system can address various error scenarios (errors concentrated in overlap regions vs. distributed errors) more effectively than a single unified static approach.
Data Source
AI summary
A device includes a memory, an error correction code (ECC) decoder, and an ECC input adjuster. The ECC decoder is configured to perform a first decode operation to decode a first portion of a representation of data read from the memory based on one or more decode parameters and to perform a second decode operation to decode a second portion of the representation of data based on one or more adjusted decode parameters. The ECC input adjuster is configured to adjust one or more decode parameters to set the one or more adjusted decode parameters based on a count of bits of the first portion that are erroneous.