Iterative ECC Decoder Scheduling Using Soft-Input Reliability

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Solution Overview

Problem

Existing error correction coding (ECC) decoding methods, such as Low Density Parity Check (LDPC) codes, face inefficiencies in iterative decoding processes due to the lack of effective scheduling schemes that optimize processing and skipping of variable-node circuits based on reliability levels, leading to increased decoding latency and power consumption.

Innovation Solution

A decoder system with logic circuitry and multiple Variable-Node Circuits (VNCs) that assigns reliability levels to code word variables, determines a processing schedule based on these levels, and decides whether to process or skip VNCs during iterations, using predefined thresholds and score calculations to optimize bit-flipping and reduce unnecessary computations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If all variable-node circuits are processed in every iteration of iterative decoding, then decoding accuracy is improved, but decoding latency and power consumption increase

Engineering Contradiction:
Improvedecoding accuracyVSAvoiddecoding latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent changes the processing parameter by introducing reliability levels (e.g., high reliability vs. low reliability) for different variable nodes based on channel conditions. The scheduler dynamically adjusts which variable nodes are processed in each iteration based on these reliability levels, avoiding unnecessary processing of high-reliability nodes while ensuring low-reliability nodes receive adequate processing attention, thus reducing decoding latency without sacrificing accuracy.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies local quality by treating different variable nodes differently based on their individual reliability characteristics. Instead of uniform processing, the system identifies specific variable nodes with low reliability and prioritizes their processing, while skipping or reducing processing of high-reliability nodes, thereby optimizing the overall decoding performance with reduced computational overhead.

Inventive Principle:
Principle #3Local quality

2Reliability

If all variable-node circuits are processed in every iteration of iterative decoding, then decoding accuracy is improved, but power consumption increases

Engineering Contradiction:
Improvedecoding accuracyVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent introduces reliability-level-based parameter changes that control the processing intensity for different variable nodes. By categorizing variable nodes into high and low reliability groups and adjusting the processing schedule accordingly, the system reduces the number of iterations and operations required for high-reliability nodes, directly lowering power consumption while maintaining decoding accuracy through focused processing of critical low-reliability nodes.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies partial action by selectively processing only the necessary subset of variable nodes (those with low reliability) rather than all variable nodes in each iteration. This partial processing approach is sufficient to achieve the required decoding accuracy while significantly reducing the computational workload and associated power consumption.

Inventive Principle:
Principle #16Partial or excessive action

3Productivity

If variable-node circuits are selectively skipped based on reliability levels, then decoding efficiency is improved, but complexity of scheduling increases

Engineering Contradiction:
Improvedecoding efficiencyVSAvoidscheduling complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by pre-determining the reliability levels of variable nodes before the iterative decoding process begins. The scheduler uses these pre-assigned reliability levels to create a processing schedule, avoiding the need for complex real-time decisions during decoding. This preliminary classification simplifies the scheduling logic while maintaining high decoding efficiency.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12052033B2Scheduling of iterative decoding depending on soft inputs
Publication Date: 2024.07.30 APPLE INC
  • US12052033B2 patent drawing
  • US12052033B2 patent drawing
  • US12052033B2 patent drawing

AI summary

A decoder includes circuitry and multiple Variable-Node Circuits (VNCs). The VNCs individually hold one or more variables of an Error Correction Code (ECC) that is representable by a plurality of check equations defined over the variables. The circuitry is configured to receive a code word including variables having m-bit values that was encoded using the ECC, to further receive reliability levels assigned respectively to the variables, to decode the code word by applying to the code word a sequence of iterations, including deciding in a given iteration whether a given VNC is to be processed or skipped in that iteration, depending on the reliability levels assigned to the variables of the given VNC, and, when the given VNC is selected for processing, to make a decision whether or not to update one or more of the variables of the given VNC, and to apply the decision by the given VNC.