ECC Decoder Read Strategy for Faster Soft-Decision Memory Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing error correction codes (ECC) in non-volatile memory devices face challenges such as requiring large memory spaces for parity data and lengthy error correction times, especially when using soft decision (SD) values which necessitate multiple read operations.
Innovation Solution
The implementation of a memory controller with an ECC decoder that employs a coarse SD read command to obtain both hard decision (HD) and soft decision (SD) data during a single read, allowing for preemptive decoding based on SD data and reducing the need for multiple reads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If soft decision (SD) values are used for error correction, then error correction ability is improved, but read operation time increases due to necessity of performing multiple reads
Solution Approach 1:
The patent performs a preliminary coarse SD read to obtain initial SD data before the fine SD read. This preliminary action allows the system to prepare decoding parameters in advance and potentially complete error correction without requiring the full sequence of multiple reads, thus reducing total read operation time while maintaining error correction ability
Solution Approach 2:
The patent divides the read operation into two segmented phases: a coarse SD read phase that obtains initial SD data and performs preliminary decoding, and a fine SD read phase that obtains more precise SD data. This segmentation allows the system to potentially complete error correction in the first phase, avoiding the time penalty of requiring all multiple reads
2Loss of time
If hard decision (HD) values only are used for error correction, then read operation time is reduced, but error correction ability reaches its limit
Solution Approach 1:
The patent changes the decision parameter from hard decision (binary) to soft decision (multi-level) values. By using SD data with richer information content instead of HD values, the system achieves improved error correction ability while managing read time through the segmented read approach and preemptive decoding
3Measurement precision
If multiple reads are performed to obtain SD data, then error correction precision is improved, but memory access time increases
Solution Approach 1:
The system performs a preliminary coarse SD read that provides sufficient precision for many error correction cases. By completing decoding with this preliminary data before initiating additional reads, the system achieves good error correction precision while minimizing memory access time
Solution Approach 2:
The patent implements a dynamic read strategy where the system adapts the number of reads performed based on the results of preliminary decoding. If errors are corrected successfully with coarse SD data, no additional reads are performed. If correction fails, then finer precision reads are dynamically initiated, optimizing the balance between precision and time
Data Source
AI summary
A memory controller includes a processor, which is configured to determine one of a first operation mode and a second operation mode as an operation mode based on a lifespan or retention of a memory device. The processor is configured to transmit to the memory device, a read command for obtaining hard decision (HD) data and a first piece of SD data during a time period of a single read, or a read command for obtaining a second piece of SD data from a plurality of reads. A decoding circuit is configured to perform iterative decoding based on the first piece of SD data or the second piece of SD data. The first operation mode is for sequentially transmitting the coarse SD read command and the fine SD read command to the memory device, whereas the second operation mode is for transmitting the fine SD read command.