ECC Decoder Memory Control With Coarse-Fine Soft Reads
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Solution Overview
Problem
Existing error correction codes (ECC) in non-volatile memory devices face challenges such as requiring large memory space for parity data and long correction times, especially when using hard decision (HD) values, while soft decision (SD) values necessitate multiple reads, leading to inefficiencies.
Innovation Solution
An ECC decoder and memory controller that utilize both hard decision (HD) and soft decision (SD) data to preemptively perform decoding, employing a coarse SD read command to obtain initial data followed by fine SD read command if necessary, optimizing decoding operations based on the device's lifespan and read count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hard decision (HD) values are used for ECC, then correction ability is improved, but correction time becomes excessively long
Solution Approach 1:
The patent performs preliminary error correction using soft decision (SD) values before final hard decision (HD) correction. By preemptively correcting easily correctable errors with SD data, the system reduces the workload for subsequent HD correction, thereby shortening total correction time while maintaining high correction ability.
Solution Approach 2:
The error correction process is divided into two segments: first, soft decision correction is applied to correctable errors; second, hard decision correction is applied to remaining errors. This segmentation allows each correction stage to be optimized independently, improving overall efficiency without sacrificing correction capability.
2Productivity
If soft decision (SD) values are used for ECC, then correction speed is improved, but multiple reads are required increasing complexity
Solution Approach 1:
The patent applies soft decision correction partially - only to the extent needed for correctable errors. By using SD values selectively for preliminary correction rather than requiring multiple full reads, the system achieves fast correction speed while minimizing the number of read operations and overall system complexity.
3Reliability
If traditional ECC is used, then error correction is performed, but large memory space is required for parity data
Solution Approach 1:
The patent changes the parameter of error correction by introducing soft decision values that provide additional information about signal reliability. This parameter change allows more efficient error correction with reduced parity overhead, as SD values enable better discrimination of errors without requiring proportionally more storage space.
Data Source
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AI summary
A memory controller includes a processor, which is configured to determine one of a first operation mode and a second operation mode as an operation mode based on a lifespan or retention of a memory device. The processor is configured to transmit to the memory device, a read command for obtaining hard decision (HD) data and a first piece of SD data during a time period of a single read, or a read command for obtaining a second piece of SD data from a plurality of reads. A decoding circuit is configured to perform iterative decoding based on the first piece of SD data or the second piece of SD data. The first operation mode is for sequentially transmitting the coarse SD read command and the fine SD read command to the memory device, whereas the second operation mode is for transmitting the fine SD read command.