Dynamic ECC Decoder Switching for High-BER Read Latency

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Solution Overview

Problem

Existing multi-gear ECC decoders experience increased decoding latency due to the need to switch from a fast low power decoder to a slow high power decoder for high-bit error rate operations, which reduces mean throughput and read performance.

Innovation Solution

Implement a controller that dynamically switches between slow high power and fast low power decoders during the decoding process based on predetermined factors, allowing transitions between power levels to optimize decoding efficiency and reduce latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a slow high power decoder is used to decode codewords with high bit error rate, then decoding accuracy is improved, but decoding latency increases and throughput decreases

Engineering Contradiction:
Improvedecoding accuracyVSAvoiddecoding latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements dynamic decoder selection that adapts to the actual error conditions of incoming codewords. The system monitors syndrome weight and error patterns in real-time, switching between fast low-power decoder and slow high-power decoder based on the detected error characteristics, rather than using a fixed decoder for all codewords

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes operational parameters by adjusting which decoder is active based on syndrome weight thresholds and error rate measurements. When syndrome weight indicates low error probability, the fast decoder is used; when syndrome weight exceeds thresholds or error patterns suggest high BER, the system transitions to the slow high-power decoder

Inventive Principle:
Principle #35Parameter changes

2Productivity

If a fast low power decoder with high parallelism is used, then decoding speed and power efficiency are improved, but decoding accuracy for high-bit error rate codewords deteriorates

Engineering Contradiction:
Improvedecoding speedVSAvoiddecoding accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system dynamically adjusts decoder selection based on real-time monitoring of syndrome weight and error patterns. The fast low-power decoder operates for normal conditions, but the system transitions to slow high-power decoder when error indicators exceed predefined thresholds, ensuring both speed and accuracy are optimized for actual conditions

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent introduces an intermediary control mechanism that monitors decoding progress and error characteristics, determining when to switch between decoders. This intermediary layer analyzes syndrome weight and error patterns to make intelligent decisions about decoder selection, preventing premature or incorrect decoder choices

Inventive Principle:
Principle #24Intermediary (Mediator)

3Measurement precision

If decoder switching is performed based on syndrome weight calculation, then decoder selection accuracy is improved, but system complexity and computational overhead increase

Engineering Contradiction:
Improvedecoder selection accuracyVSAvoidsystem complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The system performs preliminary syndrome weight calculation and error pattern analysis before committing to a decoder selection. By evaluating key parameters upfront and comparing them against predefined thresholds, the system makes informed decoder choices without requiring complex real-time analysis during the decoding process itself

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback mechanisms where the system monitors decoding outcomes and error patterns, using this information to adjust decoder selection strategies. The feedback from syndrome weight calculations and decoding success/failure rates refines the switching decisions, improving accuracy while maintaining manageable complexity through learned thresholds

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12444439B2ML assisted dynamic decoding gear selection
Publication Date: 2025.10.14 SANDISK TECHNOLOGIES LLC
  • US12444439B2 patent drawing
  • US12444439B2 patent drawing
  • US12444439B2 patent drawing

AI summary

A multi-gear ECC decoder includes a high power decoder and a low power decoder. In order to significantly reduce the decoding time for high-BER codewords using a slow high power decoder, rather than decoding codewords in either slow high power or fast low power, a controller switches between slow high power decoding and fast low power decoding during the decoding process. The controller first will determine, based on a predetermined factor, whether to start decoding in slow high power or fast low power. Once a decoding power is determined, then the decoding will begin. During the decoding process the decoding transitions from a first power lever decoder to a second power level decoder. The decoding will continue in the second decoding power level after the transition, until the decoding is completed or if another switch needs to occur for insufficient decoding.