ECC Circuit Decoding Modes for Multi-Bit DRAM Error Correction

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Semiconductor memory devices, particularly DRAMs, face increasing bit errors and yield decreases due to shrinking fabrication design rules, necessitating improved error correction capabilities.

Innovation Solution

An ECC circuit is implemented in semiconductor memory devices to generate syndromes based on parity bits using parity check matrices, enabling correction of (t1+t2) error bits through selective decoding modes, enhancing error correction capability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If fabrication design rules are shrunk to increase integration density, then device integration capacity is improved, but bit error rate increases and yield decreases

Engineering Contradiction:

Improveintegration densityVSAvoidbit error rate

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent applies preliminary action by performing ECC encoding before data is written to memory and ECC decoding after data is read from memory. The syndrome generation circuit proactively checks for errors by computing syndromes from read data and parity bits, and the correction circuit is ready to correct errors before data is used. This preliminary preparation of error correction mechanisms prevents the reliability deterioration caused by shrunk fabrication rules.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If on-chip ECC capability is enhanced to correct more error bits, then error correction capability is improved, but device complexity increases

Engineering Contradiction:

Improveerror correction capabilityVSAvoidECC circuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the ECC functionality into distinct modular components: an encoder that generates parity bits during write operations, a syndrome generation circuit that computes syndromes during read operations, and a correction circuit that corrects errors. This segmentation allows each component to be optimized independently and enables the system to achieve enhanced error correction capability (correcting up to t1+t2 error bits) without proportionally increasing overall device complexity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The syndrome generation circuit serves multiple functions: it generates syndromes for error detection, works with different parity check matrices (first and second matrices for different coding rates), and supports both single-error correction and multi-error correction modes. This multi-functionality allows the circuit to achieve enhanced error correction capability while reusing the same hardware resources, thereby limiting the increase in device complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUSRE50742E1Error correction code circuits, semiconductor memory devices and memory systems

Publication Date: 2026.01.06 SAMSUNG ELECTRONICS CO LTD

AI summary

An error correction code (ECC) circuit of a semiconductor memory device includes a syndrome generation circuit and a correction circuit. The syndrome generation circuit generates syndrome based on a message and first parity bits in a codeword read from a memory cell array by using one of a first parity check matrix and a second parity check matrix, in response to a decoding mode signal. The correction circuit receives the codeword, corrects at least a portion of (t1+t2) error bits in the codeword based on the syndrome and outputs a corrected message. Here, t1 and t2 are natural numbers, respectively.