ECC Signal Delay Compensation for Multi-Region Memory Checks
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Solution Overview
Problem
The increasing data transmission speed in semiconductor devices leads to higher error probabilities during data transmission, necessitating additional devices and methods for ensuring reliability, particularly in scenarios where data is transmitted between memory regions with differing delay amounts and times.
Innovation Solution
An electronic device is designed to compensate for differences in delay amounts and times between error check signals by using a replica delay circuit to generate delayed error check signals and an error sum signal generation circuit to sum these signals, ensuring reliable error detection and correction across memory regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transmission speed is increased to improve productivity, then the operating speed of the semiconductor device is improved, but the probability of error occurring during data transmission increases, worsening reliability
Solution Approach 1:
The patent applies preliminary action by generating error check codes (ECC/CRC) before data transmission and storing them in advance in buffer memory. This allows error detection and correction to be performed on previously transmitted data without interrupting the high-speed data flow, thus maintaining high productivity while ensuring reliability through pre-computed error protection mechanisms.
Solution Approach 2:
The patent introduces intermediary components including buffer memory for storing error check codes, dedicated error detection circuits, and error correction circuits that act as mediators between the high-speed data transmission path and the reliability verification process. These intermediaries enable parallel processing of data and error checking, resolving the contradiction between speed and reliability.
2Device complexity
If error check signals from memory regions at different locations are summed without delay compensation, then the error check operation is simplified, but the difference in delay amounts and time between error check signals causes incorrect error detection, worsening reliability
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the delay amount of error check signals based on their source memory region's location and transmission path characteristics. The delay compensation amount is calculated and applied to synchronize signals from different memory regions before summation, ensuring that all error check signals arrive at the summing circuit at the same reference time, thus maintaining reliability without excessive complexity.
3Reliability
If delay compensation is applied to synchronize error check signals from different memory regions, then the reliability of error check operation is improved, but additional delay control circuits and complexity are introduced, worsening device complexity
Solution Approach 1:
The patent calculates and stores the required delay compensation amounts in advance for each memory region based on their locations and transmission characteristics. This preliminary calculation eliminates the need for complex real-time delay adjustment circuits, as the delay amounts are predetermined and can be implemented using simple programmable delay elements or lookup tables, thus achieving reliability improvement with minimal added complexity.
Solution Approach 2:
The system implements self-service by having each memory region or error check signal path automatically determine its own required delay compensation based on pre-stored calibration data. The delay control circuits are configured to automatically adjust without requiring complex external control logic, allowing the system to self-synchronize error check signals with minimal additional circuitry.
Data Source
AI summary
An electronic device includes a replica delay circuit configured to generate a delayed error check signal by delaying a first error check signal including error information of first data stored in a first memory region. The electronic device also includes an error sum signal generation circuit configured to generate an error sum signal by summing a second error check signal including error information of second data stored in a second memory region and the delayed error check signal.