ECC Circuit Determinant Optimization for Sporadic Defect Correction
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Solution Overview
Problem
Existing semiconductor devices, such as DRAM, face challenges in efficiently correcting sporadic defective bits post-packaging, as traditional methods like replacement with redundant circuits are ineffective, and existing error correction codes (ECC) do not specify the determinant used for encoding and decoding, affecting operation speed.
Innovation Solution
A semiconductor device with an ECC control circuit that uses a determinant to generate error determination signals and syndromes, allowing for efficient error correction by specifying error locations within the data, thereby improving the ECC's operation speed and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If replacement with redundant word line or redundant bit line is used, then defective bits due to defective word line or bit line are relieved, but sporadic defective bits occurring after packaging cannot be relieved
Solution Approach 1:
The invention segments the error correction approach by dividing defective bits into two categories: those correctable by redundant word/bit lines and sporadic defective bits requiring ECC. This segmentation allows each method to be applied to its appropriate target, resolving the contradiction between reliable correction and adaptability to different defect types
Solution Approach 2:
The invention introduces ECC as an intermediary mechanism that works in conjunction with redundant word/bit lines. The ECC circuit acts as a mediator that handles sporadic defective bits that the redundant line method cannot address, thereby extending the overall system's ability to handle various defect types
2Reliability
If existing ECC is used without specifying determinant, then error correction function is provided, but operation speed is affected due to circuit configuration dependence on determinant
Solution Approach 1:
The invention changes the parameter of the determinant used in ECC operations. By selecting a specific determinant (H matrix) with optimized properties, the circuit configuration can be standardized and optimized for high-speed operation while maintaining effective error correction functionality
Solution Approach 2:
The invention performs preliminary selection and optimization of the determinant (H matrix) before ECC operations. By pre-defining the determinant structure, the circuit can be designed with fixed, optimized configurations that maximize operation speed without compromising error correction capability
Data Source
AI summary
An apparatus may comprise an ECC circuit configured to receive read data from a memory cell array to correct, an error bit contained in a data portion of the read data responsive, at least in part, to a parity portion of the read data, to generate a plurality of first error determination signals and a plurality of second error determination signals. Each of the plurality of first error determination signals provided in common to n data terminals and corresponding to an associated one of burst data of m bits. Each of the plurality of second error determination signals provided in common to the burst data of m bits and corresponding to an associated one of the n data terminals. The error bit of the data portion of the read data is detected based, at least in part, on the first error determination signals and the second error determination signals.