ECC Circuit Using Dual Polynomials for Low-Complexity Memory Decoding
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in correcting errors due to increased operating speeds and data volume, necessitating efficient error correction codes that reduce calculation complexity while maintaining error correction capabilities.
Innovation Solution
An error correction code circuit utilizing a Galois field GF(2^m) with specific generator polynomials for both FEC and CRC decoding operations, designed to minimize calculation complexity and improve hardware efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction codes are used in high-speed semiconductor memory devices, then error correction capability is maintained, but calculation complexity and hardware manufacturing complexity increase
Solution Approach 1:
The patent changes the mathematical parameters of the error correction code by using a specific generator polynomial g(x) = x^8 + x^7 + x^6 + x^4 + 1 over GF(2^8) with carefully selected coefficients. This parameter optimization reduces the computational complexity of syndrome calculation and error correction operations while maintaining the ability to detect and correct errors in high-speed memory devices
2Measurement precision
If advanced error correction algorithms are implemented to handle increased data volume, then error detection accuracy is improved, but power consumption increases
Solution Approach 1:
The patent extracts and utilizes the mirror symmetry property of the generator polynomial coefficients (where coefficients satisfy specific relationships) to simplify the syndrome calculation process. By exploiting this inherent mathematical property, the circuit performs error detection with reduced computational steps, thereby lowering power consumption while maintaining high error detection accuracy in high-speed memory operations
3Reliability
If complex generator polynomials are used for both FEC and CRC decoding, then error correction performance is improved, but hardware manufacturing complexity increases
Solution Approach 1:
The patent designs a unified error correction code circuit that simultaneously performs both FEC (Forward Error Correction) and CRC (Cyclic Redundancy Check) decoding functions using a single generator polynomial structure. This multi-functional design integrates error correction and error detection capabilities into one hardware circuit, improving error correction performance while reducing manufacturing complexity compared to implementing separate FEC and CRC circuits
Data Source
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AI summary
An error correction code circuit (100) for correcting an error of a codeword based on an element of a Galois field GF(2m), wherein m is an integer comprises a forward error correction, FEC, decoder (122) configured to substitute the element into a first generator polynomial with respect to a first primitive polynomial, among primitive polynomials having a leading term m, that has a calculation complexity less than a reference value, correct the error of the codeword based on a result of the first generator polynomial, and output an error-corrected cyclic redundancy check, CRC, codeword; and a CRC decoder (121) configured to substitute the element into a second generator polynomial with respect to a second primitive polynomial among the primitive polynomials that has a calculation complexity less than the reference value and is different from the first primitive polynomial, detect an error of the CRC codeword based on a result of the second generator polynomial, and output an error-detected message. The second generator polynomial follows g2x=∑i=02tcrcgi2xi where tcrc denotes a number of error-detectable symbols of the CRC decoder (121, 1400), and coefficients gi2 of the second generator polynomial satisfy gs2=g2tcrc−s2, where 0 ≤ s ≤ tcrc - 1.