ECC Circuit Timing Margin via Dummy Parity and Data Delay
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Solution Overview
Problem
Semiconductor apparatuses face increased bit error rates due to higher operating speeds, necessitating improved error correction mechanisms to maintain reliability and timing margins in ECC operations.
Innovation Solution
An error correction code circuit that generates a second parity signal and syndrome information, using internally generated dummy parity signals during write operations and read parity signals during read operations, with data processing circuits delaying data to compensate for timing differences and correct errors in semiconductor apparatuses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If operating speed is increased, then productivity is improved, but bit error rate increases
Solution Approach 1:
The patent applies preliminary action by generating dummy parity signals in advance during write operations and preparing read parity signals before read operations. This pre-preparation allows the ECC circuit to immediately correct errors when they occur during high-speed operations, thereby maintaining reliability while enabling increased operating speeds.
Solution Approach 2:
The patent introduces dummy parity signals as intermediaries during write operations and read parity signals as intermediaries during read operations. These intermediary signals facilitate error correction without interfering with the high-speed data transmission, thus resolving the contradiction between speed and reliability.
2Productivity
If operating speed is increased, then productivity is improved, but timing margin is reduced
Solution Approach 1:
The data processing circuit performs preliminary actions by delaying data in advance during write operations and delaying both data and parity signals during read operations. This pre-delaying synchronizes the timing of signals before they enter the ECC circuit, eliminating timing conflicts and maintaining adequate timing margins even at high operating speeds.
Solution Approach 2:
The system performs self-service timing adjustment by automatically delaying signals within the data processing circuit based on the operational mode (write or read). This internal timing self-correction ensures that timing margins are maintained without requiring external timing control, enabling high-speed operation.
3Loss of time
If dummy parity signal is used during write operation, then timing margin is improved, but device complexity increases
Solution Approach 1:
The data processing circuit performs multiple functions: it delays data during write operations, delays data and parity signals during read operations, and generates dummy parity signals when needed. By making this single circuit multi-functional, the patent achieves timing margin improvement without proportionally increasing device complexity.
Solution Approach 2:
The patent merges the functions of data delay, parity signal delay, and dummy parity signal generation into a single data processing circuit. This consolidation reduces overall circuit complexity compared to having separate circuits for each function, while still achieving the desired timing margin improvement.
Data Source
AI summary
A semiconductor apparatus includes a parity operation circuit, a write latch circuit, a data processing circuit and a write path. The parity operation circuit generates a parity signal by performing an operation on operation source data. The write latch circuit generates a write parity signal by latching the parity signal according to a delayed write signal. The data processing circuit outputs write data as the operation source data in a write operation, and delays the operation source data by a time required for operation of the parity signal and outputs it as delayed data. The write path writes the delay data and the write parity signal to a memory area in the write operation.