ECC Circuit Timing Margin Using Dummy Parity on High-Speed Memory Writes
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Solution Overview
Problem
The increasing operating speed of semiconductor apparatuses leads to a higher bit error rate, necessitating improved error correction mechanisms to enhance the reliability of ECC operations.
Innovation Solution
An error correction code circuit that generates a second parity signal and syndrome information during both write and read operations, utilizing internally generated dummy parity signals during writes and read parity signals during reads, and includes a data processing circuit to delay data accordingly, ensuring timely parity signal generation and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the operating speed of semiconductor apparatus is increased, then productivity is improved, but the bit error rate increases
Solution Approach 1:
The patent generates the second parity signal in advance during write operations using an internal dummy parity signal, so that the parity signal is ready before the actual data write completes. This preliminary generation of parity information allows the system to maintain high operating speeds while ensuring error correction capability is prepared ahead of time, resolving the conflict between speed and reliability.
2Productivity
If the operating speed is increased, then productivity is improved, but the timing margin for ECC operations is reduced
Solution Approach 1:
The error correction code circuit performs preliminary generation of the second parity signal during write operations, and performs both second parity signal generation and syndrome information generation during read operations. This advance preparation of error correction information ensures that ECC operations are completed within the available time window even at high operating speeds, maintaining adequate timing margin.
Solution Approach 2:
The patent separates the parity signal generation into different stages: first parity signal generation (external or internal), second parity signal generation (always performed by the ECC circuit), and syndrome information generation (performed during read operations). This segmentation allows each stage to be optimized independently, with critical path operations performed in advance, thereby improving overall timing margin while maintaining high operating speed.
3Reliability
If error correction mechanisms are enhanced to reduce bit errors, then reliability is improved, but device complexity increases
Solution Approach 1:
The error correction code circuit is designed to perform multiple functions: generating first parity signals (when not externally provided), generating second parity signals, generating syndrome information, and performing error correction. By making the ECC circuit universal and capable of handling multiple ECC operations within a single integrated structure, the patent achieves enhanced error correction capability without proportionally increasing device complexity.
Data Source
AI summary
In an embodiment, an error correction code circuit is provided. The error correction code circuit includes an error correction code engine and data processing circuit. The error correction code engine is configured to generate a second parity signal and syndrome information by performing an operation on operation source data and a first parity signal. The data processing circuit is configured to output write data as the operation source data and output an internally generated dummy parity signal as the first parity signal during a write operation, and to output read data as the operation source data and output a read parity signal as the first parity signal during a read operation.