ECC Logic Path Using Dynamic XOR Gates for Sub-Cycle Delay
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Solution Overview
Problem
High-frequency memory devices face significant logic delay in calculating and comparing error correcting codes (ECCs), which exceeds one clock cycle, necessitating a reduction in clock frequency to minimize delay, but this reduces bandwidth.
Innovation Solution
Implementing a logic path that uses dynamic logic gates to complete ECC calculations and comparisons independently of clock cycles, allowing for faster processing by enabling dynamic XOR gates to calculate and compare ECC values without clock cycle alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If static logic gates clocked by flip flops are used to calculate and compare ECC values, then the calculation can be synchronized with clock cycles, but the logic delay exceeds one clock cycle, reducing bandwidth
Solution Approach 1:
The patent transitions from static logic gates clocked by flip-flops to dynamic logic gates that operate without clock cycle synchronization. The dynamic logic path allows ECC calculation and comparison to complete in less than one clock cycle, enabling the system to maintain high-frequency operations while reducing logic delay. This dynamic approach eliminates the synchronization overhead that previously caused the delay to exceed one clock cycle.
2Loss of time
If clock frequency is reduced to minimize ECC calculation delay, then logic delay decreases to within one clock cycle, but bandwidth is reduced
Solution Approach 1:
The patent changes the operational parameters of the ECC logic from synchronous (clocked) to asynchronous (dynamic) operation. By using dynamic logic gates that evaluate signals without waiting for clock edges, the system achieves sub-clock-cycle delay completion. This parameter change allows the maintenance of high clock frequencies without incurring the penalty of extended logic delay, thereby preserving bandwidth.
3Speed
If dynamic logic gates are used to complete ECC calculations independently of clock cycles, then processing speed increases with delay less than one clock cycle, but clock synchronization is lost
Solution Approach 1:
The patent segments the memory interface into two independent paths: a dynamic logic path for ECC calculation and comparison that operates asynchronously with sub-clock-cycle speed, and a separate command decoding path that maintains clock synchronization. The dynamic path processes ECC signals through dynamic XOR gates and logic gates without clock constraints, while the command decoder remains synchronized. This segmentation allows the system to achieve high processing speed in the ECC path without compromising the stability and synchronization of the command path.
Data Source
AI summary
Error correcting codes (ECCs) have been proposed to be used in high frequency memory devices to detect errors in signals transmitted between a memory controller and a memory device. For high frequency memory devices, ECCs have delay characteristics of greater than one clock cycle. When the delay exceeds one clock cycle but is much less than two clock cycles, an entire second clock cycle must be added. By calculating and comparing the ECC value in a static logic circuit and a dynamic logic circuit, the logic delay is substantially reduced. In addition, the ECC value may be calculated and compared using two sets of static logic gates, where the second static logic gate is clocked by a clock signal that is delayed relative to the clock signal of the first set of logic gates.